Conferences in DBLP
David A. Patterson , Krste Asanovic , Aaron B. Brown , Richard Fromm , Jason Golbus , Benjamin Gribstad , Kimberly Keeton , Christoforos E. Kozyrakis , David Martin , Stylianos Perissakis , Randi Thomas , Noah Treuhaft , Katherine A. Yelick Intelligent RAM (IRAM): The Industrial Setting, Applications and Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald A. Rohrer A Brief History of the Future of Semiconductor Electronic Design Automation. [Citation Graph (0, 0)][DBLP ] Conf ] Gabriel P. Bischoff , Karl S. Brace , Samir Jain , Rahul Razdan Formal Implementation Verification of the Bus Interface Unit for the Alpha 21264 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Matt Kaufmann , Carl Pixley Intertwined Development and Formal Verification of a 60x Bus Model. [Citation Graph (0, 0)][DBLP ] Conf ] Bishop Brock , Warren A. Hunt Jr. Formally Specifying and Mechanically Verifying Programs for the Motorola Complex Arithmetic Processor DSP. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir BIST-Based Fault Diagnosis in the Presence of Embedded Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Yong Seok Kang , Jong Cheol Lee , Sungho Kang Built-in Self Test for Contect Addressable Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Nur A. Touba , Edward J. McCluskey Pseudo-Random Pattern Testing of Bridging Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Serban Bruma , Ralph H. J. M. Otten Novel Simulation of Deep-Submicron MOSFET Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hoon Choi , Seung Ho Hwang Time-Stamped Transition Density for the Estimation of Delay Dependent Switching Activities. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin Chen , Ivailo Nedelchev Power Compiler: A Gate-Level Power Optimization and Synthesis System. [Citation Graph (0, 0)][DBLP ] Conf ] Maria-Dana Tarlescu , Kevin B. Theobald , Guang R. Gao Elastic History Buffer: A Low-Cost Method to Improve Branch Prediction Accuracy. [Citation Graph (0, 0)][DBLP ] Conf ] I-Cheng K. Chen , Chih-Chieh Lee , Matt Postiff , Trevor N. Mudge Design Optimization for High-speed Per-address Two-level Branch Predictors. [Citation Graph (0, 0)][DBLP ] Conf ] Carl Burch PA-8000: A Case Study of Static and Dynamic Branch Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Ramsey W. Haddad , Lukas P. P. P. van Ginneken , Narendra V. Shenoy Discrete Drive Selection for Continuous Sizing. [Citation Graph (0, 0)][DBLP ] Conf ] Peichen Pan Continuous Retiming: Algorithms and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Arvind K. Karandikar , Peichen Pan , C. L. Liu Optimal Clock Period Clustering for Sequential Circuits with Retiming. [Citation Graph (0, 0)][DBLP ] Conf ] Rakesh Mehrotra , Massoud Pedram , Xunwei Wu Comparison between nMos Pass Transistor logic style vs. CMOS Complementary Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas C. Cangellaris , W. Pinello , Albert E. Ruehli Circuit-Based Description and Modeling of Electromagnetic Noise Effects in Packaged Low-Power Electronics. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Dharchoudhury , David Blaauw , Joe Norton , Satyamurthy Pullela , J. Dunning Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Xingbin Zhang , Ali Dasdan , Martin Schulz , Rajesh K. Gupta , Andrew A. Chien Architectural Adaptation for Application-Specific Locality Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Minoru Inamori , Kenji Ishii , Akihiro Tsutsui , Kazuhiro Shirakawa , Hiroshi Nakada , Toshiaki Miyazaki A New Processor Architecture for Digital Signal Transport Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jeroen A. J. Leijten , Jef L. van Meerbergen , Adwin H. Timmer , Jochen A. G. Jess PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia. [Citation Graph (0, 0)][DBLP ] Conf ] Mauricio Breternitz Jr. , Roger Smith Enhanced Compression Techniques to Simplify Programm Decompression and Execution. [Citation Graph (0, 0)][DBLP ] Conf ] R. V. K. Pillai , Dhamin Al-Khalili , Asim J. Al-Khalili A Low Power Approach to Floating Point Adder Design. [Citation Graph (0, 0)][DBLP ] Conf ] Yun-Nan Chang , Janardhan H. Satyanarayana , Keshab K. Parhi Design and Implementation of Low-Power Digit-Serial Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Khurram Muhammad , Kaushik Roy On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares Solution. [Citation Graph (0, 0)][DBLP ] Conf ] Shervin Hojat , Paul Villarrubia An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Hirendu Vaishnav , Chi-Keung Lee , Massoud Pedram Post Layout Speed-up by Event Elimination. [Citation Graph (0, 0)][DBLP ] Conf ] Ashih D. Mehta , Yao-Ping Chen , Noel Menezes , D. F. Wong , Lawrence T. Pileggi Clustering and Load Balancing for Buffered Clock Tree Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Ravishankar Arunachalam , Florentin Dartu , Lawrence T. Pileggi CMOS Gate Delay Models for General RLC Loading. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. Shepard , S. Carey , Daniel K. Beece , Robert F. Hatch , Gregory A. Northrop Design Methodology for the High-Performance G4 S/390. [Citation Graph (0, 0)][DBLP ] Conf ] Charles F. Webb , John S. Liptay A High-Frequency Custom CMOS S/390 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] James D. Warnock , Leon J. Sigal , Brian W. Curran , Yuen H. Chan High-Performance CMOS Circuit Techniques for the G-4 S/390 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] A. Tuminaro A 400MHz, 144Kb CMOS ROM Macro for an IBM S/390-Class Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Castañeda , Xiaodong Zhang , James M. Hoover Jr. A Comparative Evaluation of Hierarchical Network Architecture of the HP-Convex Exemplar. [Citation Graph (0, 0)][DBLP ] Conf ] Hitoshi Oi , N. Ranganathan Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Kozuch , Wayne Wolf , Andrew Wolfe An Approach to Network Caching for Multimedia Objects. [Citation Graph (0, 0)][DBLP ] Conf ] W. K. Luk , Y. Katayama , Wei Hwang , M. Wordeman , T. Kirihata , Akashi Satoh , Seiji Munetoh , H. Wong , B. El-Kareh , P. Xiao , Rajiv V. Joshi Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Akihiro Takamura , Masashi Kuwako , Masashi Imai , Taro Fujii , Motokazu Ozawa , Izumi Fukasaku , Yoichiro Ueno , Takashi Nanya TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Davey , David Lloyd An Evaluation of Asynchronous and Synchronous Design for Superscalar Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Fu-Chiung Cheng Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] David S. Bormann , Peter Y. K. Cheung Asnchronous Wrapper for Heterogeneous Systems. [Citation Graph (0, 0)][DBLP ] Conf ] William H. Joyner Jr. Design and Test: The Lost World. [Citation Graph (0, 0)][DBLP ] Conf ] Somesh Jha , Yuan Lu , Marius Minea , Edmund M. Clarke Equivalence Checking Using Abstract BDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Meinel , Anna Slobodová Speeding up Variable Reordering of OBDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev K. Ranjan , Wilsin Gosti , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions. [Citation Graph (0, 0)][DBLP ] Conf ] Zhongcheng Li , Yuhong Zhao , Yinghua Min , Robert K. Brayton Timed Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios Kagaris , Spyros Tragoudas , Dimitrios Karayiannis Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald D. Blanton , John P. Hayes Properties of the Input Pattern Fault Model. [Citation Graph (0, 0)][DBLP ] Conf ] Fulvio Corno , Paolo Prinetto , Maurizio Rebaudengo , Matteo Sonza Reorda , Giovanni Squillero A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yanbing Li , Miodrag Potkonjak , Wayne Wolf Real-Time Operating Systems for Embedded Computing. [Citation Graph (0, 0)][DBLP ] Conf ] David L. Rhodes , Wayne Wolf Allocation and Data Arrival Design of Hard Real-time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Allara , S. Filipponi , William Fornaciari , Fabio Salice , Donatella Sciuto Improving Design Turnaround Time via Two-Levels Hw/Sw Co-Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Chirag S. Patel , Sek M. Chai , Sudhakar Yalamanchili , David E. Schimmel Power Constrained Design of Multiprocessor Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Soderquist , Miriam Leeser Memory Traffic and Data Cache Behavior of an MPEG-2 Software Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] José A. Tierno , Prabhakar Kudva Asynchronous Transpose-Matrix Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Wai-Chi Fang , Guang Yang , Bedabrata Pain , Bing J. Sheu A Low Power Smart Vision System Based on Active Pixel Sensor Integrated with Programmable Neural Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Alan J. Hu , Masahiro Fujita , Chris Wilson Formal Verification of the HAL S1 System Cache Coherence Protocol. [Citation Graph (0, 0)][DBLP ] Conf ] Jawahar Jain , Amit Narayan , Masahiro Fujita , Alberto L. Sangiovanni-Vincentelli A Survey of Techniques for Formal Verification of Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] William Canfield , E. Allen Emerson , Avijit Saha Checking Formal Specifications under Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Karim Arabi , Bozena Kaminska Built-In Temperature Sensors for On-line Thermal Monitoring of Microelectronic Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Ping Wang , Chin-Long Wey Development of Hierarchical Testability Design Methodologies for Analog/Mixed-Signal Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Chen , Akhileswaran Ramachandran A Novel Test Set Design for Parametric Testing of Analog and Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Fung Yu Young , D. F. Wong On the Construction of Universal Series-Parallel Functions for Logic Module Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jörn Stohmann , Erich Barke A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Wai-Kei Mak , D. F. Wong Channel Segmentation Design for Symmentrical FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Chenxi Zhang , Xiaodong Zhang , Yong Yan Multi-Column Implementations for Cache Associativity. [Citation Graph (0, 0)][DBLP ] Conf ] Lizy Kurian John , Akila Subramanian Design and Performance Evaluation of a Cache Assist to implement Selective Caching. [Citation Graph (0, 0)][DBLP ] Conf ] Jude A. Rivers , Edward S. Tam , Edward S. Davidson On Effective Data Supply For Multi-Issue Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. Shepard Practical Issues of Interconnect Analysis in Deep Submicron Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Wilfrido A. Moreno , Fernando J. Falquez , John R. Samson Jr. , Thomas Smith First Test Results of System Level Fault Tolerant Design Validation Through Laser Fault Injection. [Citation Graph (0, 0)][DBLP ] Conf ] Craig Hunter Integrated Diagnostics for Embedded Memory Built-in Self Test on Power PCTM Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiana Bolchini , Donatella Sciuto , Fabio Salice A TSC Evaluation Function for Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Tung Chen , Kayhan Küçükçakar An Architectural Power Optimization Case Study using High-level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Rusell E. Henning , Chaitali Chakrabarti High-Level Design Synthesis of a Low Power, VLIW Processor for the IS-54 VSELP Speech Encoder. [Citation Graph (0, 0)][DBLP ] Conf ] Jih-Kwon Peir , Windsor W. Hsu Fast Cache Access with Full-Map Block Directory. [Citation Graph (0, 0)][DBLP ] Conf ] Preeti Ranjan Panda , Hiroshi Nakamura , Nikil D. Dutt , Alexandru Nicolau A Data Alignment Technique for Improving Cache Performance. [Citation Graph (0, 0)][DBLP ] Conf ] I-Cheng K. Chen , Chih-Chieh Lee , Trevor N. Mudge Instruction Prefetching Using Branch Prediction Information. [Citation Graph (0, 0)][DBLP ] Conf ] Randy H. Katz Is Wireless Data Dead? [Citation Graph (0, 0)][DBLP ] Conf ] X. Tan , J. Tong , P. Tan , Nohpill Park , Fabrizio Lombardi An Efficient Multi-Way Algorithm for Balanced Partitioning of VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory Tumbush , Dinesh Bhatia Partitioning Under Timing and Area Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Chandy , Prithviraj Banerjee A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Hai Zhou , D. F. Wong Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Kowen Lai , Christos A. Papachristou , Mikhail Baklashov High Level Test Synthesis Across the Boundary of Behavioral and Structural Domains. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Yang Jou , Ming-Chang Nien Power Driven Partial Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh C. Tekumalla , Premachandran R. Menon Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. [Citation Graph (0, 0)][DBLP ] Conf ] M. Bacis , Giacomo Buonanno , Fabrizio Ferrandi , Franco Fummi , Luca Gerli , Donatella Sciuto Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Brunvand , Steven M. Nowick , Kenneth Y. Yun Practical Advances in Asynchronous Design. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Mehrotra , Shaz Qadeer , Rajeev K. Ranjan , Randy H. Katz Benchmarking and Analysis of Architectures for CAD Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Keshab K. Parhi Fast Low-Energy VLSI Binary Addition. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Suzuki , Hiroshi Makino , Koichiro Mashiko , Hisanori Hamano A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Yamin Li , Wanming Chu Parallel-Array Implementations of a Non-Restoring Square Root Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Maitham Shams , Jo C. Ebergen , Mohamed I. Elmasry Optimizing CMOS Implementations of the C-element. [Citation Graph (0, 0)][DBLP ] Conf ] Rakefet Kol , Ran Ginosar A Double-Latched Asynchronous Pipeline. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Hwang , Rajiv V. Joshi , Walter H. Henkels A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Norman Chang , Valery Kanevsky , O. Sam Nakagawa , Khalid Rahmat , Soo-Young Oh Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] David Li , Andrew Pua , Pranjal Srivastava , Uming Ko A Repeater Optimization Methodology for Deep Sub-Micron, High Performance Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Zhang Zhu , Bradley S. Carlson Critical Voltage Transition Logic: An Ultrafast CMOS Logic Family. [Citation Graph (0, 0)][DBLP ] Conf ] Aurobindo Dasgupta , Shantanu Ganguly Divide & Conquer: A Strategy for Synthesis of Low Power Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan-Yu Wang , Kaushik Roy Estimation of Maximum Power for Sequential Circuits Considering Spurious Transitions. [Citation Graph (0, 0)][DBLP ] Conf ] Sriram Govindarajan , Ranga Vemuri Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] 