Conferences in DBLP
David May How to Design a Parallel Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Fritz H. Gaensslen , David D. Meyer Liquid Nitrogen CMOS for Computer Applications. [Citation Graph (0, 0)][DBLP ] Conf ] E. Scott Kirkpatrick Neural Networks Update. [Citation Graph (0, 0)][DBLP ] Conf ] Vishwani D. Agrawal Design and Test-The Two Sides of a Coin. [Citation Graph (0, 0)][DBLP ] Conf ] Yooichi Shintani , Kiyoshi Inoue , Toru Shonai , K. Wada , S. Abe , Katsuro Wakai Logic Design for a High Performance Mainframe Computer, The HITAC M-880 Processor. [Citation Graph (0, 0)][DBLP ] Conf ] A. Shacham , Y. Levy , Z. Bronstein , E. Loewenstein , D. M. Bruck , D. Deitcher Architectural Considerations for SF-core Based Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Juergen Froessl , Bernhard Eschermann Module Generation for AND/XOR Fields (XPLAs). [Citation Graph (0, 0)][DBLP ] Conf ] Jin-fuw Lee A Layout Compaction Algorithm with Multiple Grid Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Eero Pajarre , Tapani Ritoniemi , Hannu Tenhunen Methods and Algorithms for Converting IC Designs Between Incompatible Design Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yosinori Watanabe , Robert K. Brayton Incremental Synthesis for Engineering Changes. [Citation Graph (0, 0)][DBLP ] Conf ] Kuang-Chien Chen , Masahiro Fujita Concurrent Resynthesis for Network Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Robert F. Damiano , Len Berman Dual Global Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Joan Villoldo , Prathima Agrawal , Vishwani D. Agrawal Stafan Algorithms for MOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gianpiero Cabodi , Silvano Gai , Matteo Sonza Reorda Fast Differential Fault Simulation by Dynamic Fault Ordering. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Trotter , Richard Evans A Fine Grain Architecture for Parallel Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Sujit Dey , Franc Brglez , Gershon Kedem Partitioning Sequential Circuits for Logic Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunwoo Cho , Gary D. Hachtel , Fabio Somenzi Redundancy Identification and Removal Based on Implicit State Enumeration. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Lin , A. Richard Newton Implicit Manipulation of Equivalence Classes Using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Retiming of Circuits with Single Phase Transparent Latches. [Citation Graph (0, 0)][DBLP ] Conf ] F. Sebastiã G. dos Santos , Jacobus W. Swart Modeling fo Interconnections Lines for Stimulation of VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas H. Krodel PowerPlay-Fast Dynamic Power Estimation Based on Logic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Yen-Cheng Wen , Kyle Gallivan , Resve A. Saleh Parallel Event-Driven Waveform Relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Przemyslaw Bakowski , Jean-Luc Dubois , Adam Pawlak A Technique for Generating Efficient Simulators. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Wen Wu , Shyue-Kung Lu Designing Self-Testable Cellular Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Long Wey Concurrent Error Detection in Array Dividers by Alternating Input Data. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Jay Hsu , Bing J. Sheu , Sudhir M. Gowda Testing of Analog Neural Array-Processor Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Lon-Chan Chu Fault-Tolerant Model of Neural Computing. [Citation Graph (0, 0)][DBLP ] Conf ] M. Hanawa , Tadahiko Nishimukai , O. Nishii , M. Suzuki , K. Yano , M. Hiraki , S. Shukuri , T. Nishida On-Chip Multiple Superscalar Processors with Secondary Cache Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Leith Johnson , Rob Horning , Larry Thayer , Daniel Li , Rob Snyder System Level ASIC Design for Hewleet-Packard's Low Cost PA-RISC Workstations. [Citation Graph (0, 0)][DBLP ] Conf ] Moshe Shahaf DesignFab: A Methodology for ULSI Microprocessor Design. [Citation Graph (0, 0)][DBLP ] Conf ] Maximo H. Salinas , Barry W. Johnson , James H. Aylor Implementation-Independent Model of an Instruction Set Architecture Using VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] George J. Klir Fuzzy Logic: Why the U.S. Falls Behind?. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth R. Traub , Gregory M. Papadopoulos , Michael J. Beckerle , James E. Hicks , Jonathan Young Overview of the Monsoon Project. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher F. Joerg , G. Andrew Boughton The Monsoon Interconnection Network. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Beckerle , Gregory M. Papadopoulos Test and Validation for Monsoon Processing Elements. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng An Effective Analog Approach to Steiner Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Andrew B. Kahng , Gabriel Robins , Majid Sarrafzadeh , C. K. Wong Performance-Driven Global Routing for Cell Based ICs. [Citation Graph (0, 0)][DBLP ] Conf ] James P. Cohoon , L. J. Randall Critical Net Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Hon F. Li , S. C. Leung , P. N. Lam Synthesis of Delay-Insensitive Circuits by Refinements into Atomic Threads. [Citation Graph (0, 0)][DBLP ] Conf ] Mark E. Dean , David L. Dill , Mark Horowitz Self-Timed Logic Using Current-Sensing Completion Detection (CSCD). [Citation Graph (0, 0)][DBLP ] Conf ] Steven M. Nowick , David L. Dill Synthesis of Asynchronous State Machines Using A Local Clock. [Citation Graph (0, 0)][DBLP ] Conf ] I. Deol , Chittaranjan Mallipeddi , T. Ramakrishnan Amdahl Chip Delay Test System. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick C. McGeer Robust Path Delay-Fault Testability on Dynamic CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Chatterjee , Manuel A. d'Abreu Syndrome-Based Functional Delay Fault Location in Linear Digital Data-Flow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiyuki Tamura , Shinji Komori , Fumiyasu Asai , Hirono Tsubota , Hisakazu Sato , Hidehiro Takata , Yoshihiro Seguchi , Takeshi Tokuda , Hiroaki Terada A Data-Driven Architecture for Distributed Parallel Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Robert H. Payne , José G. Delgado-Frias MPU: A N-Tuple Matching Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Maresca , Pierpaolo Baglietto Transitive Closure and Graph Component Labeling on Realistic Processor Arrays Based on Reconfigurable Mesh Network. [Citation Graph (0, 0)][DBLP ] Conf ] Hsin-Chou Chi , Yuval Tamir Decomposed Arbiters for Large Crossbars with Multi-Queue Input Buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Eduard Cerny A Compositional Transformation for Formal Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Carl Pixley , Gary Beihl , Ernesto Pacas-Skewes Automatic Derivation of FSM Specification to Implementation Encoding. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , Kurt Keutzer , A. S. Krishnakumar Design Verfication and Reachability Analysis Using Algebraic Manipulation. [Citation Graph (0, 0)][DBLP ] Conf ] Pranav Ashar , Abhijit Ghosh , Srinivas Devadas Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Paul S. Levy Power-Down Structures for BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Sami A. Al-Arian , Hussam Y. Abujbara , Jim C. Ruel A Unique Approach to Built-in-Self-Test Circuit Design. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis , M. Boudjit New Implementations, Tools, and Experiments for Decreasing Self-Checking PLAs Area Overhead. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Chiu , Christos A. Papachristou A Built-In Self-Testing Approach for Minimizing Hardware Overhead. [Citation Graph (0, 0)][DBLP ] Conf ] Craig Gleason , Mark Forsyth , Charlie Kohlhardt , Steve Mangelsdorf , Barry Arnold , Rick Luebs CMOS Processor Circuit Design in Hewlett-Packard's Series 700 Workstations. [Citation Graph (0, 0)][DBLP ] Conf ] C. K. Tien , C. C. Poon , Hans J. Greub , Jack F. McDonald F-RISC/I: Fast Reduced Instruction Set Computer with GaAs (H)MESFET Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] K. Nah , Robert F. Philhower , J. S. Van Etten , S. Simmons , V. Tsinker , James Loy , Hans J. Greub , Jack F. McDonald F-RISC/G: AlGaAs/GaAs HBT Standard Cell Library. [Citation Graph (0, 0)][DBLP ] Conf ] Peter R. Nuth , William J. Dally A Mechanism for Efficient Context Switching. [Citation Graph (0, 0)][DBLP ] Conf ] K. Glasmacher , A. Hess , Gerhard Zimmermann A Genetic Algorithm for Global Improvement of Macrocell Layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Massoud Pedram , Kamal Chaudhary , Ernest S. Kuh I/O Pad Assignment Based on the Circuit Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Kei-Yong Khoo A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Raymond Peck , Jay Patel Design Methodology for a MIPS Compatible Embedded Control Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Darren Jones , Rongken Yang , Mark Kwong , George Harper Verification Techniques for a MIPS Compatibvle Embedded Control Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Bob Culk , Sanjay Desai , Moshe Gavrielov , George Harper , Darren Jones , Mark Kwong , Marlon Murzello , Tim Oke , Jay Patel , Raymond Peck , James Wei , Rongken Yang The Architecture of the LR33000: A MIPS Compatible RISC Processor for Embedded Control Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Genoe , Luc J. M. Claesen , Eric Verlind , Frank Proesmans , Hugo De Man Illustration of the SFG-Tracing Multi-Level Behavioral Verification Methodology, by the Correctness Proof of a High to Low Level Synthesis Application in CATHEDRAL-II. [Citation Graph (0, 0)][DBLP ] Conf ] Michael C. McFarland , Thaddeus J. Kowalski Specifying System Behavior in CPA. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Aagaard , Miriam Leeser A Formally Verified System for Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Geetani Edirisooriya , John P. Robinson Aliasing Probability in Multiple Input Linear Signature Automata for Q-ary Symmetric Errors. [Citation Graph (0, 0)][DBLP ] Conf ] Anita Gleason , Wen-Ben Jone Reduced Hamming Count and Its Aliasing Probability. [Citation Graph (0, 0)][DBLP ] Conf ] John C. Chan , Baxter F. Womack , D. F. Wong On the Manisfestation of Faults to Errors in Signature Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Katsumata , Hidekazu Tokunaga , Seiji Yasunobu Operation Method in Fuzzy Set Operation Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Vicente Fuentes-Sánchez , Peter Y. K. Cheung A Tag Coprocessor Architecture for Symbolic Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Chie Dou , Shao-Ming Wu An Efficient Pattern Match Architecture for Production Systems Using Content-Addressable Memory. [Citation Graph (0, 0)][DBLP ] Conf ] J. Morris Chang , Edward F. Gehringer Object-Caching for Performance in Object-Oriented Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Pradip Bose Early Performance Estimation of Super Scalar Machine Models. [Citation Graph (0, 0)][DBLP ] Conf ] Sankaran Karthik , Indira de Souza , Joseph T. Rahmeh , Jacob A. Abraham Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Athanas , Harvey F. Silverman An Adaptive Hardware Machine Architecture and Compiler for Dynamic Processor Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Lennart Lindh , Frank Stanischewski FASTCHART-Idea and Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Walling R. Cyre Mapping Design Knowledge from Multiple Representations. [Citation Graph (0, 0)][DBLP ] Conf ] Janaki Akella , Kenneth L. McMillan Synthesizing Converters Between Finite State Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Sato , Masaharu Imai , Tetsuya Hakata , Alauddin Y. Alomary , Nobuyuki Hikichi An Integrated Design Environment for Application Specific Integrated Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-In Henry Chen Allocation of Multiport Memory with Ports of Different Type in Register Transfer Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski , Alexander Albicki Random Testability of Redundant Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gert-Jan Tromp , A. J. van de Goor Logic Synthesis of 100-percent Testable Logic Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Ernst , P. Nowottnick Fault Tolerant VLSI Design with Functional Block Redundancy. [Citation Graph (0, 0)][DBLP ] Conf ] James D. Meindl Design and Test Automation-Gigascale Integration (GSI) in the 21st Century. [Citation Graph (0, 0)][DBLP ] Conf ] Quentin G. Schmierer , Andrew H. Wottreng IBM AS/400 Processor Architecture and Design Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Robert F. Lembach , John M. Borkenhagen , John R. Elliott , Randall A. Schmidt VLSI Design Automation for the Application System/400. [Citation Graph (0, 0)][DBLP ] Conf ] Dennis T. Cox , Charles L. Johnson , Bruce G. Rudolph , David W. Siljenberg , Robert R. Williams IBM AS/400 Processor Technology. [Citation Graph (0, 0)][DBLP ] Conf ] James Pardey , Martin Bolton Logic Synthesis of Synchronous Parallel Controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Christos A. Papachristou , Scott Chiu , Haidar Harmanani SYNTEST: A Method for High-Level SYNthesis with Self-TESTability. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Hsing Chen , Chienwen Wu , Daniel G. Saab Accessibility Analysis on Data Flow Graph: An Approach to Design for Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Chai Huang , John Willis , Tim Schmitt Fine-Line Printed Circuit Board for High-Performance Computer Design. [Citation Graph (0, 0)][DBLP ] Conf ] Amit P. Agrawal , Chi Shih Chang , Debra A. Gernhart Design Considerations for Digital Circuit Interconnections in a Multilayer Printed Circuit Board. [Citation Graph (0, 0)][DBLP ] Conf ] Keith Nabors , S. Kim , Jacob White , Stephen D. Senturia Fast Capacitance Extraction of General Three-Dimensional Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Walter B. Marvin , Wayne Burleson A Simulator for General Purpose Optical Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Alex G. Dickinson , M. M. Downs An Optical Multichip Module. [Citation Graph (0, 0)][DBLP ] Conf ] Joongho Choi , Bing J. Sheu A GaAs Receiver Module for Optoelectronic Computing and Interconnection. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Fu Chang , David G. Messerschmitt VLSI Designs for High-Speed Huffman Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] C. Thomas White , Raj K. Singh , Peter B. Reintjes , Jordan Lampe , Bruce W. Erickson , Wayne D. Dettloff , Vernon L. Chi , Stephen F. Altschul BioSCAN: A VLSI-Based System for Biosequence Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] H. Bonnenberg , Andreas Curiger , Norbert Felber , Hubert Kaeslin , Xuejia Lai VLSI Implementation of a New Block Cipher. [Citation Graph (0, 0)][DBLP ] Conf ] Cheng-Hsi Chen , Ioannis G. Tollis An Optimal Algorithm for Spiral Floorplan Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Khe-Sing The , D. F. Wong Area Optimization for Higher Order Hierarchical Floorplans. [Citation Graph (0, 0)][DBLP ] Conf ] Susmita Sur-Kolay , Bhargab B. Bhattacharya The Cycle Structure of Channel Graphs in Nonslicible Floorplans and A Unified Algorithm for Feasible Routing Order. [Citation Graph (0, 0)][DBLP ] Conf ] Kyunrak Chong , Sartaj Sahni Flipping Modules to Minimize Maximum Wire Length. [Citation Graph (0, 0)][DBLP ] Conf ] A. Barish , J. Eckhardt , M. Mayo , W. Svarczkopf , S. Gaur , Rao R. Tummala High Performance Packaged Electronics for the IBM ES9000TM Mainframe. [Citation Graph (0, 0)][DBLP ] Conf ] W. J. Nohilly , V. T. Lund IBM ES/9000TM System Architecture and Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] R. S. Belanger , David P. Conrady , P. S. Honsinger , T. J. Lavery , S. J. Rothmann , E. C. Schanzenbach , D. Sitaram , C. R. Selinger , R. E. DuBois , G. W. Mahoney , G. F. Miceli Enhanced Chip/Package Design for the IBM ES/9000TM . [Citation Graph (0, 0)][DBLP ] Conf ] Brion L. Keller , David A. Haynes Design Automation of Test for the EX/9000TM Series Processors. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Harding , Tomás Lang , Jeong-A. Lee A Comparison of Redundant CORDIC Rotation Engines. [Citation Graph (0, 0)][DBLP ] Conf ] N. Burgess A Fast Division Algorithm for VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Hosahalli R. Srinivas , Keshab K. Parhi High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation. [Citation Graph (0, 0)][DBLP ] Conf ] Behrooz Parhami New Classes of Unidirectional Error-Detecting Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Niraj K. Jha , Sying-Jyan Wang Design and Synthesis of Self-Checking VLSI Circuits and Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Stanislaw J. Piestrak Design of a Self-Testing Checker for Borden Code. [Citation Graph (0, 0)][DBLP ] Conf ] Robert F. Miracky , T. Bishop , Claire T. Galanakis , H. Hashemi , Tom J. Hirsch , S. Madere , Heinrich G. Müller , T. Rudwick , L. Smith , Scott C. Sommerfeldt , B. Weigler Technologies for Rapid Prototyping of Multi-Chip Modules. [Citation Graph (0, 0)][DBLP ] Conf ] James B. Burr , Allen M. Peterson Energy Considerations in Multichip-Module Based Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Rudi Hendel The Commercial Realization of Multi-Chip Modules Quo Vadimus. [Citation Graph (0, 0)][DBLP ] Conf ] Somchai Kittichaikoonkit , Michitaka Kameyama , Tatsuo Higuchi High-Performance VLSI Processor for Robot Inverse Dynamics Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Ricardo Telichevesky , Prathima Agrawal , John A. Trotter A New O(n log n) Scheduling Heuristic for Parallel Decomposition of Sparce Matrices. [Citation Graph (0, 0)][DBLP ] Conf ] Liang-Gee Chen , Wai-Ting Chen , Yen-Shen Jehng , Tzi-Dar Chiueh A Predictive Parallel Motion Estimation Algorithm for Digital Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] John A. Trotter , Prathima Agrawal A Multiprocessor Architecture for Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Abdul A. Malik , David Harrison , Robert K. Brayton Three-Level Decomposition with Application to PLDs. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan Saul An Algorithm for the Multi-Level Minimazation of Reed-Muller Rpresentations. [Citation Graph (0, 0)][DBLP ] Conf ] Yun-Cheng Ju , Resve A. Saleh Identification of Viable Paths Using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Karem A. Sakallah , Trevor N. Mudge , Timothy M. Burks , Edward S. Davidson Optimal Clocking of Circular Pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] 