Conferences in DBLP
Randal E. Bryant Symbolic Analysis Methods for Masks, Circuits, and Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel P. Siewiorek Wearable Computers: Merging Information Space with the Workspace. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas W. Williams Design for Testability: Today and in the Future. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Langevin , Eduard Cerny A Recursive Technique for Computing Lower-Bound Performance of Schedules. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Hu , Ahmed Ghouse , Bradley S. Carlson Lower Bounds on the Iteration Time and the Number of Resources for Functional Pipelined Data Flow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Samit Chaudhuri , Robert A. Walker , John Mitchell The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Rodney Boleyn , James Debardelaben , Vivek Tiwari , Andrew Wolfe A Split Data Cache for Superscalar Processors. [Citation Graph (0, 0)][DBLP ] Conf ] André Seznec About Set and Skewed Associativity on Second-Level Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Honesty C. Young , Eugene J. Shekita An Intelligent I-Cache Prefetch Mechanism. [Citation Graph (0, 0)][DBLP ] Conf ] Pinhong Chen , Jyuo-Min Shyu , Liang-Gee Chen Hardware Verification Using Symbolic State Transition Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Sofiène Tahar , Ramayya Kumar Towards a Methodology for the Formal Hierarchical Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Vishakantaiah , Thomas Thomas , Jacob A. Abraham , Magdy S. Abadir AMBIANT: Automatic Generation of Behavioral Modifications for Testability. [Citation Graph (0, 0)][DBLP ] Conf ] João P. Marques Silva , Karem A. Sakallah An Analysis of Path Sensitization Criteria. [Citation Graph (0, 0)][DBLP ] Conf ] Hsi-Chuan Chen , Siu-Wing Cheng , Yaun-Chung Hsu , David Hung-Chang Du A Path Sensitization Approach to Area Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Horng-Fei Jyu , Sharad Malik Statistical Timing Optimization of Combinatorial Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth D. Boese , Andrew B. Kahng , Bernard A. McCoy , Gabriel Robins Fidelity and Near-Optimality of Elmore-Based Routing Constructions. [Citation Graph (0, 0)][DBLP ] Conf ] Trung A. Diep , Mikko H. Lipasti , John Paul Shen Architecture-Compatible Code Boosting for Performance Enhancement of the IBM RS/6000. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas M. Conte , William H. Mangione-Smith Determining Cost-Effective Multiple Issue Processor Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Chia-Jiu Wang , Frank Emnett Area and Performance Comparison of Pipelined RISC Processors Implementing Different Precise Interrupt Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Hideki Ando , Chikako Nakanishi , Hirohisa Machida , Tetsuya Hara , Satoru Kishida , Masao Nakaya Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Raymond Roth , John Watkins , Michael Hsieh , William Radke , Donald Hejna , Richard Tom , Byung Kim An Integrated Environment for Concurrent Development of a Pixel Processor ASIC and Application Software. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrich Holtmann , Rolf Ernst Speculative Computation for Coprocessor Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] J. Morris Chang , Edward F. Gehringer Evaluation of an Object-Caching Coprocessor Design for Object-Oriented Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Burleson , Jason Ko , Douglas Niehaus , Krithi Ramamritham , John A. Stankovic , Gary Wallace , Charles C. Weems The Spring Scheduling Co-Processor: A Scheduling Accelerator. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Chiu , Christos A. Papachristou A Partial Scan Cost Estimation Method at the System Level. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Bhatia , Niraj K. Jha Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaodong Xie , Alexander Albicki Bit-Splitting for Testability Enhancement in Scan-Based Design. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Long Wey , Ming-Der Shieh , P. David Fisher ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tod Amon , Henrik Hulgaard , Steven M. Burns , Gaetano Borriello An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Enric Pastor , Jordi Cortadella An Efficient Unique State Coding Algorithm for Signal Transition Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Auletta , Robert B. Reese , Cherrice Traver A Comparison of Synchronous and Asynchronous FSMD Designs. [Citation Graph (0, 0)][DBLP ] Conf ] N. Ranganathan , Raghu Sastry , R. Venkatesan , Joseph W. Yoder , David C. Keezer SMAC: A Scene Matching Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Ted Kehl Hardware Self-Tuning and Circuit Performance Monitoring. [Citation Graph (0, 0)][DBLP ] Conf ] Jien-Chung Lo Fault-Tolerant Content Addressable Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Debabrata Ghosh , S. K. Nandy A 400 MHz Wave-Pipelined 8 X 8-Bit Multiplier in CMOS Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Makino , Yasunobu Nakase , Hirofumi Shinohara A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Hosahalli R. Srinivas , Bapiraju Vinnakota , Keshab K. Parhi A C-Testable Carry-Free Divider. [Citation Graph (0, 0)][DBLP ] Conf ] Telle Whitney , Jeff Schlageter A New High Performance Field Programmable Gate Array Family. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Roy , Sudip Nag , Santanu Dutta Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jagannathan Narasimhan , Kazuo Nakajima A Reconfiguration-Based Yield Enhancement System. [Citation Graph (0, 0)][DBLP ] Conf ] C. Norris Ip , David L. Dill Efficient Verification of Symmetric Concurrent Systems. [Citation Graph (0, 0)][DBLP ] Conf ] P. A. Subrahmanyam , Josep M. Espinalt , Meng-Lin Yu Specification and Synthesis of Mixed-Mode Systems: Experiments in a VHDL Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Fujita , Shinji Kono Synthesis of Controllers from Interval Temporal Logic Specification. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Brodnax , Mike Schiffli , Floyd Watson The PowerPC 601 Design Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Susumu Narita , Fumio Arakawa , Kunio Uchiyama , Ikuya Kawasaki Design Methodology for GMICROTM /500 TRON Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Avtar Saini Design of the Intel PentiumTM Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Skaf , Alain Guyot VLSI Design of On-Line Add/Multiply Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Gong Guo , Mohammad Ashtijou A Note About the Correction Cycle of High Radix Booth's Multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Dhananjay S. Phatak , Israel Koren , Hoon Choi Hybrid Number Representations with Bounded Carry Propagation Chains. [Citation Graph (0, 0)][DBLP ] Conf ] Toshikazu Sakano , Takao Matsumoto , Kazuhiro Noguchi A Three-Dimensional Mesh Multiprocessor System Using Board-to-Board Free-Space Optical Interconnects: COSINE-III. [Citation Graph (0, 0)][DBLP ] Conf ] Tzi-cker Chiueh A Vector Memory System Based on Wafer-Scale Integrated Memory Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] K. Ishibashi , T. Hayashi , T. Doi , N. Masuda , A. Yamagiwa , T. Okabe A Novel Clock Distribution System for CMOS VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Jaehong Park , M. Ray Mercer An Efficient Symbolic Design Verification System. [Citation Graph (0, 0)][DBLP ] Conf ] Gianpiero Cabodi , Paolo Camurati Exploiting Cofactoring for Efficient FSM Symbolic Traversal Based on the Transition Relation. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhat Jain , Ganesh Gopalakrishnan Hierarchical Constraint Solving in the Parametric Form with Applications to Efficient Symbolic Simulation Based Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Weidong Li , Carl McCrosky , Mostafa H. Abd-El-Barr Reducing the Cost of Test Pattern Generation by Information Reusing. [Citation Graph (0, 0)][DBLP ] Conf ] Rathish Jayabharathi , Thomas Thomas , Earl E. Swartzlander Jr. A Comparative Evaluation of Adders Based on Performance and Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Ravindranath Naiknaware Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design Environment. [Citation Graph (0, 0)][DBLP ] Conf ] John Watkins , Raymond Roth , Michael Hsieh , William Radke , Donald Hejna , Byung Kim , Richard Tom A Memory Controller with an Integrated Graphics Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Tzi-cker Chiueh Trail: A Track-Based Logging Disk Architecture for Zero-Overhead Writes. [Citation Graph (0, 0)][DBLP ] Conf ] Lishing Liu Multiple-Page Translation for TLB. [Citation Graph (0, 0)][DBLP ] Conf ] Perng-Shyong Lin , Charles A. Zukowski Analysis and Control of Timing Jitter in Digital Logic Arising from Noise Voltage Sources. [Citation Graph (0, 0)][DBLP ] Conf ] Anirudh Devgan , Ronald A. Rohrer ACES: A Transient Simulation Strategy for Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Michael A. Riepe , João P. Marques Silva , Karem A. Sakallah , Richard B. Brown Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Ti-Yen Yen , Wayne Wolf Optimal Scheduling of Finite-State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Usha Prabhu , Barry M. Pangrle Global Mobility Based Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Tang Chang , Kenneth Rose , Robert A. Walker Cluster-Oriented Scheduling in Pipelined Data Path Syntesis. [Citation Graph (0, 0)][DBLP ] Conf ] Jer-Min Jou , Shiann-Rong Kuang Library-Adaptively Integrated Data Path Synthesis for DSP Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chryssa Dislis , Anthony P. Ambler , I. D. Dear , J. H. Dick Economics in Design and Test. [Citation Graph (0, 0)][DBLP ] Conf ] B. R. Wilkins , C. Shi Design Guidelines and Testability Assessment. [Citation Graph (0, 0)][DBLP ] Conf ] Yusuke Mishina , Keiji Kojima String Matching on IDP: A String Matching Algorithm for Vector Processors and Its Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Raghu Sastry , N. Ranganathan A Systolic Array for Approximate String Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Alex G. Dickinson , C. J. Nicol A Systolic Architecture for High Speed Pipelined Memories. [Citation Graph (0, 0)][DBLP ] Conf ] D. Scott Wills , W. Stephen Lacy , Huy Cat , Michael A. Hopper , Ashutosh Razdan , Sek M. Chai Pica: An Ultra-Light Processor for High-Througput Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Yosinori Watanabe , Lisa Guerra , Robert K. Brayton Logic Optimization with Multi-Output Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Lin , Hugo De Man Low-Power Driven Technology Mapping under Timing Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Vigyan Singhal , Yosinori Watanabe , Robert K. Brayton Heuristic Minimization of Synchronous Relations. [Citation Graph (0, 0)][DBLP ] Conf ] Kamlesh Rath , Bhaskar Bose , Steven D. Johnson Derivation of a DRAM Memory Interface by Sequential Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Paul R. Stephan , Robert K. Brayton Physically Realizable Gate Models. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Hua , Hantao Zhang Formal Semantics of VHDL for Verification of Circuit Designs. [Citation Graph (0, 0)][DBLP ] Conf ] W. Ye , Rolf Ernst , Thomas Benner , Jörg Henkel Fast Timing Analysis for Hardware-Software Co-Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Bhaskar Bose , M. Esen Tuna , Steven D. Johnson System Factorization in Codesign: A Case Study of the Use of Formal Techniques to Achieve Hardware-Software Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] K. ten Hagen , Heinrich Meyr Partitioning and Surmounting the Software-Hardware Abstraction Gap in an ASIC Design Project. [Citation Graph (0, 0)][DBLP ] Conf ] Wing Ning Li Strongly NP-Hard Discrete Gate Sizing Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey S. Salowe , David M. Warme An Exact Rectilinear Steiner Tree Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Dian Zhou , F. Tsui Neighbour State Transition Method for VLSI Optimization Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey M. Arnold , Duncan A. Buell , Dzung T. Hoang , Daniel V. Pryor , Nabeel Shirazi , Mark R. Thistle The Splash 2 Processor and Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Iseli , Eduardo Sanchez Beyond Superscalar Using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Lewis , Marcus van Ierssel , Daniel H. Wong A Field Programmable Accelerator for Compiled-Code Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Miodrag Potkonjak , Sujit Dey , Zia Iqbal , Alice C. Parker High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Lin Efficient Symbolic Support Manipulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jayashree Saxena , Dhiraj K. Pradhan Desgin for Testability of Asynchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios Kagaris , Spyros Tragoudas , Dinesh Bhatia Pseudoexhaustive BIST for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Orailoglu , Ian G. Harris Test Path Generation and Test Scheduling for Self-Testable Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Ping-Chung Li , Ibrahim N. Hajj Computer-Aided Redesign of VLSI Circuits for Hot-Carrier Reliability. [Citation Graph (0, 0)][DBLP ] Conf ] Hungse Cha , Janak H. Patel A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald D. Hindmarsh Complex Gate Performance Improvement by Jog Insertion into Transistor Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Aagaard , Miriam Leeser A Framework for Specifying and Designing Pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Todd A. Cook , Paul D. Franzon , Edwin A. Harcourt , Thomas K. Miller III System-Level Specification of Instruction Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Lyle D. Kipp , David J. Kuck Newton: Performance Improvement Through Comparative Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Shang-E Tai , Debashis Bhattacharya Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow Graph. [Citation Graph (0, 0)][DBLP ] Conf ] Naveena Nagi , Abhijit Chatterjee , Jacob A. Abraham MIXER: Mixed-Signal Fault Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Giacomo Buonanno , Franco Fummi , Donatella Sciuto Functional Fault Models and Gate Level Coverage for Sequential Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Laura Farinetti , Pier Luca Montessoro An Adaptive Technique for Dynamic Rollback in Concurrent Event-Driven Fault Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Régis Leveugle , X. Delord , Gabriele Saucier Influence of Error Correlations on the Signature Analysis Aliasing. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv Gupta Phi-Test: Perfect Hashed Index Test for Test Response Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Santhanam Srinivasan , Niraj K. Jha Efficient Diagnosis in Algorithm-Based Fault Tolerant Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] F. L. Vargas , Michael Nicolaidis , Bernard Courtois Quiescent Current Monitoring to Improve the Reliability of Electronic Systems in Space Radiation Environments. [Citation Graph (0, 0)][DBLP ] Conf ] R. J. Glaise , X. Jacquart Fast CRC Calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Chatterjee , Rabindra K. Roy Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Luc J. M. Claesen , Joan Daemen , Mark Genoe , G. Peeters Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Artur Wrzyszcz , David Milford A New Modulo 2a + 1 Multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] 