Conferences in DBLP
Abbas El Gamal Field-Programmable Integrted Circuits - Overview and Future Trends. [Citation Graph (0, 0)][DBLP ] Conf ] Derrick Meyer Alpha Architecture: Hardware Implementation and Software Programming Implications. [Citation Graph (0, 0)][DBLP ] Conf ] Aart J. de Geus High Level Design: A Design Vision for the 90's. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon D. Robinson Design and Test - The Next Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Stephanie White , Mack W. Alford , Brian McCay , David Oliver , Colin Tully , Julian Holtzman , C. Stephen Kuehl , David Owens , Allan Willey Trends in Computer-Based Systems Engineering. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Wolf , Ernest Frey Tutorial on Embedded System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Brand , Vijay S. Iyengar Identification of Single Gate Delay Fault Redundancies. [Citation Graph (0, 0)][DBLP ] Conf ] Tien-Chien Lee , Wayne Wolf , Niraj K. Jha , John M. Acken Behavioral Synthesis for Easy Testability in Data Path Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Marek A. Perkowski , Laszlo Csanky , Andisheh Sarabi , Ingo Schäfer Fast Minimization of Mixed-Polarity AND/XOR Canonical Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , Horng-Fei Jyu , Kurt Keutzer , Sharad Malik Statistical Timing Analysis of Combinational Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Lukas P. P. P. van Ginneken Fanin Ordering in Multi-Slot Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. McMillan , David L. Dill Algorithms for Interface Timing Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffery Banker Designing ASICs for Use with Multichip Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Yervant Zorian A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Gopal Lakhani VLSI Design of Modulo Adders/Subtractors. [Citation Graph (0, 0)][DBLP ] Conf ] Thou-Ho Chen , Liang-Gee Chen , Yi-Shing Chang Design of Concurrent Error-Detectable VLSI-Based Array Dividers. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Brunvand , Nick Michell , Kent F. Smith A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Charles A. Zukowski , Ying-Wen Bai Implementing a High-Frequency Pattern Generator Based on Combinational Merging. [Citation Graph (0, 0)][DBLP ] Conf ] Martine D. F. Schlag , Jackson Kong , Pak K. Chan Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Trimberger , Mon-Ren Chene Placement-Based Partitioning for Lookup-Table-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Narasimha B. Bhat , Dwight D. Hill Routable Technologie Mapping for LUT FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin Tseng , Jonathan Rose , Stephen Dean Brown Improving FPGA Routing Architectures Using Architecture and CAD Interactions. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay K. Jain , Gibert E. Perez , Earl E. Swartzlander Jr. Arithmetic Error Analysis of a new Reciprocal Cell. [Citation Graph (0, 0)][DBLP ] Conf ] Jien-Chung Lo Reliable Floating-Point Arithmetic Algorithms for Berger Encoded Operands. [Citation Graph (0, 0)][DBLP ] Conf ] Jalil Fadavi-Ardekani MxN Booth Encoded Multiplier Generator Using Optimized Wallace Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Philip E. Madrid , Brian Millar , Earl E. Swartzlander Jr. Modified Booth Algorihtm for High Radix Multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Mani B. Srivastava , Trevor I. Blumenau , Robert W. Brodersen Design and Implementation of a Robot Control System Using a Unified Hardware-Software Rapid Prototyping Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Aardoom , Paul Stravers An Application Specific Processor for a Multi-System Navigation Receiver. [Citation Graph (0, 0)][DBLP ] Conf ] Ohad Falik , Gideon D. Intrater NSC's Digital Answering Machine Solution. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Butts , Jon Batcheller , Joseph Varghese An Efficient Logic Emulation System. [Citation Graph (0, 0)][DBLP ] Conf ] James H. Aylor , Raul Camposano , Michael A. Schuette , Wayne Wolf , Nam S. Woo The Future of Embedded System Design. [Citation Graph (0, 0)][DBLP ] Conf ] T. Okabayashi , K. Kubo , Z. Hirose , K. Suzuki System Level Verification of Large Scale Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Yuzheng Ding , Andrew B. Kahng , Peter Trajmar , Kuang-Chien Chen An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chieh Chang , Malgorzata Marek-Sadowska Technology Mapping via Transformations of Function Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] T. Besson , H. Bouzouzou , M. Crastes , I. Floricica , Gabriele Saucier Synthesis on Multiplexer-Based F.P.G.A. Using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Amar Mukherjee , Jeffrey W. Flieder , N. Ranganathan MARVLE: A VLSI Chip for Variable Length Encoding and Decoding. [Citation Graph (0, 0)][DBLP ] Conf ] Baher Haroun , Elie Torbey Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] G. Mahlich , G.-H. Huaman-Bollo , J. Preißner , Johannes Schuck , Hans Sahm , P. Weingart , D. Weinsziehr , J. Yeandel One-Chip System Integration for GSM with the DSP KISS-16V2. [Citation Graph (0, 0)][DBLP ] Conf ] Soo-Young Oh , Keh-Jeng Chang , Norman Chang , Ken Lee Interconnect Modeling and Design in High-Speed VLSI/ULSI Systems. [Citation Graph (0, 0)][DBLP ] Conf ] C.-S. Li , Harald S. Stone , C. M. Olsen Fully Differential Optical Interconnects for High-Speed Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jay K. Adams , Donald E. Thomas Addressing the Tradeoff Between Standard and Custom ICs in System Level Design. [Citation Graph (0, 0)][DBLP ] Conf ] C. R. Moore , D. M. Balser , J. S. Muhich , R. E. East IBM Single Chip RISC Processor (RSC). [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Desai The Architecture of the LR33020 GraphX Processor: A MIPS-RISC Based X-Terminal Controller. [Citation Graph (0, 0)][DBLP ] Conf ] David May , Roger Shepherd , Peter Thompson The T9000 Transputer. [Citation Graph (0, 0)][DBLP ] Conf ] Raj Mittra Electromagnetic Modeling and Simulation of Electronic Packages. [Citation Graph (0, 0)][DBLP ] Conf ] Hansruedi Heeb , Albert E. Ruehli , J. Eric Bracken , Ronald A. Rohrer Three Dimensional Circuit Oriented Electromagnetic Modeling for VLSI Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Colin Gordon Time Domain Simulation of Multiconductor Transmission Lines with Frequency-Dependent Losses. [Citation Graph (0, 0)][DBLP ] Conf ] G. A. Sai-Halasz Directions in Futrue High End Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Prasad Raje Design and Scaling of BiCMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey I. Alter DACCT - Dynamic ACCess Testing of IBM Large Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok K. Chandra , Vijay S. Iyengar Constraint Slving for Test Case Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Miyako Odawara , Kazunori Kuriyama , Tadaaki Bandoh Archimedes: An Approach to Architecutre-Independent Modeling for High-Level Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-In Henry Chen , Joel T. Yuen Concurrent Test Scheduling in Built-In Self-Test Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Shujian Zhang , R. Byrne , D. Michael Miller BIST Generators for Sequential Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-In Henry Chen , Joel T. Yuen , Ji-Der Lee Autonomous-Tol for Hardware Partitioning in a Built-in Self-Test Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry R. Burch Delay Models for Verifying Speed-Dependent Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Luciano Lavagno , Alberto L. Sangiovanni-Vincentelli Linear Programming for Optimum Hazard Elimination in Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chris J. Myers , Teresa H. Y. Meng Synthesis of Timed Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Orailoglu , Ramesh Karri High-Level Synthesis of Self-Recovering MicroArchitectures. [Citation Graph (0, 0)][DBLP ] Conf ] Minjoong Rim , Rajiv Jain Estimating Lower-Bound Performance of Schedules Using a Relaxation Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Karl van Rompaey , Ivo Bolsens , Hugo De Man Just in Time Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Debra Bernstein , John F. Brown III , Rebecca L. Stamm , G. Michael Uhler NVAX and NVAX + Single-Chip CMOS VAX Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Walker Anderson Logical Verification of the NVAX CPU Chip Design. [Citation Graph (0, 0)][DBLP ] Conf ] Victor Peng , Dale R. Donchin , Yao-Tsung Yen Design Methodology and CAD Tools for the NVAX Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] James Pardey , Tomasz Kozlowski , Jonathan Saul , Martin Bolton State Assignment Algorithms for Parallel Controller Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Maya K. Yajnik , Maciej J. Ciesielski Finite State Machine Decomposition Using Multiway Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] June-Kyung Rho , Fabio Somenzi The Role of Prime Compatibles in the Minimization of Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Sequential Circuit Design Using Synthesis and Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Armin Liebchen , Ganesh Gopalakrishnan Dynamic Reordering of Hgh Latency Transactions Using a Modified a Micropipeline. [Citation Graph (0, 0)][DBLP ] Conf ] Steven M. Nowick , Kenneth Y. Yun , David L. Dill Practical Asynchronous Controller Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Y. Yun , David L. Dill , Steven M. Nowick Synthesis of 3D Asynchronous State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] N. C. Paver , P. Day , Stephen B. Furber , Jim D. Garside , J. V. Woods Register Locking in an Asynchronous Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios Kagaris , Fillia Makedon , Spyros Tragoudas On Minimizing Hardware Overhead for Pseudoexhaustive Circuit Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Sami A. Al-Arian , Musaed A. Al-Kharji Fault Simulation and Test Generation by Fault Sampling Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Niraj K. Jha , Sying-Jyan Wang , Phillip C. Gripka Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ding Lu , Carol Q. Tong Multiple Fault Detection in CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yang Cai , D. F. Wong Channel Density Minimization by Pin Permutation. [Citation Graph (0, 0)][DBLP ] Conf ] Yachyang Sun , C. L. Liu An Area Minimizer for Floorplans with L-Shaped Regions. [Citation Graph (0, 0)][DBLP ] Conf ] Pradip Bose , David LaPotin , Gopalakrishnan Vijayan , SungHo Kim Workload-Driven Floorplanning for MIPS Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Nick Tredennick Desktop Wars - The PC Versus the Workstation. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre Yakovlev On Limitations and Extensions of STG Model for Designing Asynchronous Control Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Shlomo Kipnis Analysis of Asynchronous Binary Arbitration on Digital-Transmission-Line Busses. [Citation Graph (0, 0)][DBLP ] Conf ] Tam-Anh Chu Automatic Synthesis and Verification of Hazard-Free Control Circuits from Asynchronous Finite State Machine Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] William J. Dally , Andrew A. Chien , Stuart Fiske , Greg Fyler , Waldemar Horwat , John S. Keen , Richard A. Lethin , Michael D. Noakes , Peter R. Nuth , D. Scott Wills The Message Driven Processor: An Integrated Multicomputer Processing Element. [Citation Graph (0, 0)][DBLP ] Conf ] Peter R. Nuth , William J. Dally The J-Machine Network. [Citation Graph (0, 0)][DBLP ] Conf ] Richard A. Lethin , William J. Dally MDP Design Tools and Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Margaret A. St. Pierre , Shaw-Wen Yang , Dan Cassiday Functional VLSI Design Verification Methodology for the CM-5 Massively Parallel Supercomputer. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Zak Jr. , Jeffrey V. Hill An IEEE 1149.1 Compliant Testability Architecture with Internal Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Sungho Kang , Stephen A. Szygenda Modeling and Simulation of Design Errors. [Citation Graph (0, 0)][DBLP ] Conf ] William K. C. Lam , Robert K. Brayton On Relationship Between ITE and BDD. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Te Lai , Sarma Sastry , Massoud Pedram Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Mark A. Heap , William A. Rogers , M. Ray Mercer A Synthesis Algorithm for Two-Level XOR Based Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Roy , Sharat Prasad SYCLOP: Synthesis of CMOS Logic for Low Power Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Paul T. Gutwin , Patrick C. McGeer , Robert K. Brayton Delay Prediction for Technology-Independent Logic Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Ursula Westerholz , Heinrich Theodor Vierhaus Library Mapping of CMOS-Switch-Level-Circuits by Extraction of Isomorphic Subgraphs. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Chatterjee A New Approach to Fault-Tolerance in Linear Analog Systems Based on Checksum-Coded State Space Representations. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaodong Xie , Alexander Albicki , Andrzej Krasniewski Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space Expansion. [Citation Graph (0, 0)][DBLP ] Conf ] Zhi-Jian Jiang , R. Venkatesen Theory and Design of Two-Rail Totally Self-Checking Basic Building Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Georges Quénot , Bertrand Zavidovique The ETCA Data-Flow Functional Computer for Real-Time Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Barry S. Fagin , J. Gill Watt FPGA and Rapid Prototyping Technology Use in a Special Purpose Computer for Molecular Genetics. [Citation Graph (0, 0)][DBLP ] Conf ] Smaragda Konstantinidou The Selective Extra-Stage Butterfly. [Citation Graph (0, 0)][DBLP ] Conf ] Sankaran Karthik , Jacob A. Abraham Distributed VLSI Simulation on a Network of Workstations. [Citation Graph (0, 0)][DBLP ] Conf ] Jalal A. Wehbeh , Daniel G. Saab Hierarchical Simulation of MOS Circuits Using Extracted Functional Models. [Citation Graph (0, 0)][DBLP ] Conf ] Bob Melville , Peter Feldmann , Shahriar Moinian AC++ Based Environment for Analog Circuit Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] David L. Dill , Andreas J. Drexler , Alan J. Hu , C. Han Yang Protocol Verification as a Hardware Design Aid. [Citation Graph (0, 0)][DBLP ] Conf ] Eduard Cerny Verification of I/O Trace Set Inclusion for a Class of Non-Deterministic Finite State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew D. Gordon The Formal Definition of a Synchronous Hardware-Description Language in Higher Order Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Kuehlmann , Reinaldo A. Bergamaschi High-Level State Machine Specification and Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Takahara Versioning and Concurrency Control in a Distributed Design Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Balkrishna Ramkumar , Prithviraj Banerjee ProperCAd: A Portable Object-Oriented Parallel Environment for VLSI CAD. [Citation Graph (0, 0)][DBLP ] Conf ] Lishing Liu , Jih-Kwon Peir Sampling of Cache Congruence Classes. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Nowakowski , Matthew T. O'Keefe A CRegs Implementation Study Based on the MIPS-X RISC Processor. [Citation Graph (0, 0)][DBLP ] Conf ] H. Fatih Ugurdag , Christos A. Papachristou ALMP: A Shifting Memory Architecture for Loop Pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] O. Kebichi , Michael Nicolaidis A Tool for Automatic Generation of BISTed and Transparent BISTed Rams. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Chen , Glen Sunada An Ultra-Large Capacity Single-Chip Memory Architecture With Self-Testing and Self-Repairing. [Citation Graph (0, 0)][DBLP ] Conf ] Bapiraju Vinnakota , Jason Andrews Repair of RAMs With Clustered Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy Kam , P. A. Subrahmanyam Comparing Layouts with HDL Models: A Formal Verification Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Fujita RTL Design Verification by Making Use of Datapath Information. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhat Jain , Ganesh Gopalakrishnan Some Techniques for Efficient Symbolic Simulation-Based Verification. [Citation Graph (0, 0)][DBLP ] Conf ] 