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International Conference on Computer Design (ICCD) (iccd)
1994 (conf/iccd/1994)

  1. Neil Weste
    OK, If These CAD Tools Are So Great, Why Isn't My Chip Design On Schedule?. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:2-8 [Conf]
  2. William S. Carter
    The Future of Programmable Logic and Its Impact on Digital System Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:10-16 [Conf]
  3. Prathima Agrawal
    Emerging Techologies for Electronic Design and Test. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:18- [Conf]
  4. Andreas Kuehlmann, Lukas P. P. P. van Ginneken
    Grammar-Based Optimization of Synthesis Scenarios. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:20-25 [Conf]
  5. Aiguo Lu, Jonathan Saul, Erik L. Dagless
    Architecture Oriented Logic Optimization for Lookup Table Based FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:26-29 [Conf]
  6. Yung-Te Lai, Kuo-Rueih Ricky Pan, Massoud Pedram
    FPGA Synthesis Using Function Decomposition. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:30-35 [Conf]
  7. Qinghong Wu, C. Y. Roger Chen, John M. Acken
    Efficent Boolean Matching Algorithm for Cell Libraries. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:36-39 [Conf]
  8. David J. Lilja, Shanthi Ambalavanan
    A Superassociative Tagged Cache Coherence Directory. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:42-45 [Conf]
  9. Lishing Liu
    Issues in Multi-Level Cache Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:46-52 [Conf]
  10. Jeffrey D. Gee, Alan Jay Smith
    Analysis of Multiprocessor Memory Refernce Behavior. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:53-59 [Conf]
  11. Rupinder Hundal, Vojin G. Oklobdzija
    Determination of Optimal Sizes for a First and Second Level SRAM-DRAM On-Chip Cache Combination. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:60-64 [Conf]
  12. M. Morioka, K. Kurosawa, S. Miura, T. Nakamikawa, S. Ishikawa
    Design and Evaluation of the High Performance Multi-Processor Server. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:66-69 [Conf]
  13. Sangho Ha, Junghwan Kim, Eunha Rho, Yoonhee Nah, Sangyong Han, Daejoon Hwang, Heunghwan Kim, Seung Ho Cho
    A Massively Parallel Multithreaded Architecture: DAVRID. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:70-74 [Conf]
  14. Hussain Al-Asaad, Mankuan Michael Vai, James Feldman
    Distributed Reconfiguration of Fault Tolerant VLSI Mulipipeline Arrays with Constant Interstage Path Lengths. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:75-78 [Conf]
  15. Choong Gun Oh, Hee Yong Youn
    Fault Tolerant Processor Arrays for Nonlinear Shortest Path Problem. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:79-83 [Conf]
  16. Wuudiann Ke, Premachandran R. Menon
    Delay-Verifiability of Combinational Circuits Based on Primitive Faults. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:86-90 [Conf]
  17. Sandeep Bhatia, Niraj K. Jha
    Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:91-96 [Conf]
  18. Shangzhi Sun, David Hung-Chang Du, Duen-Ren Liu
    Testability Considerations. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:97-100 [Conf]
  19. Ian G. Harris, Alex Orailoglu
    SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:101-104 [Conf]
  20. Bernd Becker, Rolf Drechsler
    OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:106-110 [Conf]
  21. Aarti Gupta, Allan L. Fisher
    Tradeoffs in Canonical Sequential Function Representations. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:111-116 [Conf]
  22. Zheng Zhu, Steven D. Johnson
    Capturing Synchronization Specifications for Sequential Compositions. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:117-121 [Conf]
  23. Chin-Long Wey
    Concurrent Error Detection in High Speed Carry-free Division Using Alternative Input Data. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:124-127 [Conf]
  24. Stanislaw J. Piestrak
    Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:128-131 [Conf]
  25. Fahad M. Alzahrani, Tom Chen
    On-Chip TEC-QED ECC for Ultra-Large, Single-Chip Memory Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:132-137 [Conf]
  26. Ray A. Kamin III, George B. Adams III, Pradeep K. Dubey
    Dynamic List-Scheduling with Finite Resources. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:140-144 [Conf]
  27. Rahul Razdan, Karl S. Brace, Michael D. Smith
    PRISC Software Acceleration Techniques. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:145-149 [Conf]
  28. Sissades Tongsima, Nelson L. Passos, Edwin Hsing-Mean Sha
    Communication Sensitive Rotation Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:150-153 [Conf]
  29. Shangzhi Sun, David Hung-Chang Du, Hsi-Chuan Chen
    Efficient Timing Analysis for CMOS Circuits Considering Data Dependent Delays. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:156-159 [Conf]
  30. R. Peset Llopis, Lluis Ribas, Jordi Carrabina
    Short Destabilizing Paths in Timing Verification. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:160-163 [Conf]
  31. Xuguang Zhang, Ramalingam Sridhar
    Synchronization of Wave-Pipelined Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:164-167 [Conf]
  32. Scott Hauck, Gaetano Borriello, Carl Ebeling
    Mesh Routing Topologies for Multi-FPGA Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:170-177 [Conf]
  33. Naohisa Ohta, Hiroshi Nakada, Kazuhisa Yamada, Akihiro Tsutsui, Toshiaki Miyazaki
    PROTEUS: Programmable Hardware for Telecommunication Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:178-183 [Conf]
  34. Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke
    Area & Time Limitations of FPGA-based Virtual Hardware. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:184-189 [Conf]
  35. John M. Borkenhagen, Glen H. Handlogten, John D. Irish, Sheldon B. Levenstein
    AS/400TM 64-bit PowerPCTM-Compatible Processor Implementaiton. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:192-196 [Conf]
  36. Mike Gruver, Nghia Phan, Tony Aipperspach, Scott Hilker, Jerry Bartley
    AS/400 PowerPCTM Compatible Semi-Custom Technology. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:197-202 [Conf]
  37. Masahito Matsuo, Hiroyuki Kondo, Yukari Takata, Souichi Kobayashi, Mitsugu Satoh, Toyohiko Yoshida, Yuichi Saitoh, Jun-ichi Hinata
    A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM Interface. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:203-210 [Conf]
  38. Ruchir Puri, Jun Gu
    Area Efficient Synthesis of Asynchronous Interface Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:212-216 [Conf]
  39. Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, Steve Temple, J. V. Woods
    The Design and Evaluation of an Asynchronous Microprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:217-220 [Conf]
  40. Prabhakar Kudva, Ganesh Gopalakrishnan, Erik Brunvand, Venkatesh Akella
    Performance Analysis and Optimization of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:221-224 [Conf]
  41. Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger
    Automatic Verification of Refinement. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:225-229 [Conf]
  42. Gianpiero Cabodi, Paolo Camurati, Stefano Quer
    Efficient State Space Pruning in Symbolic Backward Traversal. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:230-235 [Conf]
  43. Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi
    A Structural Approach to State Space Decomposition for Approximate Reachability Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:236-239 [Conf]
  44. Ellen Sentovich, Robert K. Brayton
    An Exact Optimization of Two-Level Acyclic Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:242-249 [Conf]
  45. Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    State Assignment for Power and Area Minimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:250-254 [Conf]
  46. Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton
    Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:255-261 [Conf]
  47. M. Esen Tuna, Steven D. Johnson, Robert G. Burger
    Continuations in Hardware-Software Codesign. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:264-269 [Conf]
  48. Michael Kozuch, Andrew Wolfe
    Compression of Embedded System Programs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:270-277 [Conf]
  49. Stefano Antoniazzi, Alessandro Balboni, William Fornaciari, Donatella Sciuto
    HW/SW Codesign for Embedded Telecom Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:278-281 [Conf]
  50. Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham
    A Signature Analyzer for Analog and Mixed-signal Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:284-287 [Conf]
  51. Amitava Majumdar
    WRAPTure: A Tool for Evaluation and Optimization of Weights for Weighted Random Pattern Testing. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:288-291 [Conf]
  52. Dimitrios Kagaris, Spyros Tragoudas
    A Class of Good Characteristics Polynomials for LFSR Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:292-295 [Conf]
  53. Z. Guan, P. Thomson, A. E. A. Almaini
    A Parallel CMOS 2's Complement Multiplier Based on 5: 3 Counter. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:298-301 [Conf]
  54. Edwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham
    A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:302-305 [Conf]
  55. Denis Archambaud, Pascal Faudemay
    An Arbitration Tree Adapted to Object Oriented Associative Memories. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:306-310 [Conf]
  56. Pong P. Chu, Ramana Gottipati
    Write Buffer Design for On-Chip Cache. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:311-316 [Conf]
  57. Anand Raghunathan, Niraj K. Jha
    Behavioral Synthesis for low Power. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:318-322 [Conf]
  58. Laurence Goodby, Alex Orailoglu, Paul M. Chau
    Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:323-326 [Conf]
  59. Sergei Sokolov, Ramesh Karri
    Allocation and Binding During Fault-Secure Microarchitecture Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:327-330 [Conf]
  60. Karin Högstedt, Alex Orailoglu
    Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering Microarchitectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:331-334 [Conf]
  61. E. L. Hannon, F. P. O'Connell, L. J. Shieh
    POWER2 Architecture and Performance. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:336-339 [Conf]
  62. Katherine E. Stewart, Steven W. White
    The Effects of Compiler Options on Application Performance. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:340-343 [Conf]
  63. S. Surya, Pradip Bose, Jacob A. Abraham
    Architectural Performance Verification: PowerPCTM Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:344-347 [Conf]
  64. R. Wolber, Uwe Gläser, Heinrich Theodor Vierhaus
    Testability Analysis for Test Generation in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:350-353 [Conf]
  65. Sanghyeon Baeg, William A. Rogers
    A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:354-358 [Conf]
  66. Sungho Kang, Wai-on Law, Bill Underwood
    Path-Delay Fault Simulation for a Standard Scan Design Methodology. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:359-362 [Conf]
  67. Sandip Kundu
    Multifault Testable Circuits Based on Binary Parity Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:363-366 [Conf]
  68. Kevin Covey, Sandra Murdock, Thomas R. Shiple
    Two-phase Logic Design by Hardware Flowcharts. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:368-380 [Conf]
  69. Shangzhi Sun, David Hung-Chang Du, Yaun-Chung Hsu, Hsi-Chuan Chen
    On Valid Clocking for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:381-384 [Conf]
  70. Hungse Cha, Janak H. Patel
    Latch Design for Transient Pulse Tolerance. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:385-388 [Conf]
  71. Robert E. Mains, Thomas A. Mosher, Lukas P. P. P. van Ginneken, Robert F. Damiano
    Timing Verification and Optimization for the PowerPCTM Processor Family. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:390-393 [Conf]
  72. Yao-Ping Chen, D. F. Wong
    On Retiming for FPGA Logic Module Minimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:394-397 [Conf]
  73. Samir Lejmi, Bozena Kaminska, Edouard Wagneur
    Retiming for the Global Optimization of Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:398-403 [Conf]
  74. Charles P. Roth, Ricky Lewelling, Tim Brodnax
    The PowerPCTM 604 Microprocessor Design Methodology. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:404-408 [Conf]
  75. Michael J. Garcia, Brian K. Reynolds
    Single Chip PCI Bridge and Memory Controller for PowerPCTM Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:409-412 [Conf]
  76. M. Armstead, Michael Cogswell, S. Halverson, T. Musta
    PowerPC Visual Simulator: Peeking Under the Hood of the PowerPC Engine. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:413-418 [Conf]
  77. Jack P. F. Glas, Sándor E. Skolnik
    Fourier Transform based DS/FH Spread Spectrum Receiver. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:420-423 [Conf]
  78. D. R. Woodward, D. C. Levy, R. G. Harley
    An FPGA based Configurable I/O System for AC Drive Controllers. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:424-427 [Conf]
  79. Jörg Wilberg, Raul Camposano, Ursula Westerholz, Uwe Steinhausen
    Design of an Embedded Video Compression System - A Quantitative Approach. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:428-431 [Conf]
  80. Steven M. Nowick, Bill Coates
    UCLOCK: Automated Design of High-Peformance Unclocked State Machines. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:434-441 [Conf]
  81. Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand
    Peephole Optimization of Asynchronous Macromodule Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:442-446 [Conf]
  82. Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan
    Initialization Isuues in the Synthesis of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:447-452 [Conf]
  83. Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen
    Architectural Verification of Processors Using Symbolic Instruction Graphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:454-459 [Conf]
  84. Mark Genoe, Luc J. M. Claesen, Hugo De Man
    A Parallel Method for Functional Verification of Medium and High Throughput DSP Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:460-463 [Conf]
  85. Huy Nam Nguyen, J. P. Tual, L. Ducousso, M. Thill, P. Vallet
    The Structured Logic CAD Suite Used on the DPS7000 System. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:464-467 [Conf]
  86. Faisal Haq, Samiha Mourad
    Optimal Logic Blocks for FPGAs, using Factorial Design Techniques. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:470-474 [Conf]
  87. Aditya A. Aggarwal, David M. Lewis
    Routing Architectures for Hierarchical Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:475-478 [Conf]
  88. Jason L. Kelly, Peter A. Ivey
    Defect Tolerant SRAM Based FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:479-482 [Conf]
  89. Anneliese von Mayrhauser, Richard T. Mraz, Jeff Walls, Pete Ocken
    Domain Based Testing: Increasing Test Case Reuse. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:484-491 [Conf]
  90. Raghu V. Hudli, Curtis L. Hoskins, Anand V. Hudli
    Software Metrics for Object-Oriented Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:492-495 [Conf]
  91. Luis A. Montalvo, Alain Guyot
    Combinational Digit-Set Converters for Hybrid Radix-4 Arithmetic. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:498-503 [Conf]
  92. Kiyoung Choi, KiJong Lee, Jun-Woo Kang
    A Self-Timed Divider Using RSD Number System. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:504-507 [Conf]
  93. Stanislaw J. Piestrak
    Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:508-511 [Conf]
  94. Michael Quayle, ChiLai Huang
    Complex Operator Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:514-517 [Conf]
  95. Daniel Brand, Robert F. Damiano, Lukas P. P. P. van Ginneken, Anthony D. Drumm
    In the Driver's Seat of BooleDozer. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:518-521 [Conf]
  96. Dileep Kumar, Bob Erickson
    ASOP: Arithmetic Sum-of-Products Generator. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:522-526 [Conf]
  97. H. Sato, Michihiro Yamazaki, Masahiro Fujita
    YEPHCAD and FLORA: Logic Synthesis for Control and Datapath. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:527-530 [Conf]
  98. Peter Thoma
    Future Needs for Automotive Electronics. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:532-539 [Conf]
  99. N. Ranganathan, Satish Venugopal
    A VLSI Chip for Template Matching. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:542-545 [Conf]
  100. Glen Sunada, Jain Jin, Matt Berzins, Tom Chen
    COBRA: An 1.2 Million Transistor Expandable Column FFT Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:546-550 [Conf]
  101. Dan Picker, Michael B. Bendak, Ronald D. Fellman
    A VLSI Priority Packet Queue with Overwrite and Inheritance. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:551-555 [Conf]
  102. Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pillage
    Domain Characterization of Transmission Line Models for Efficient Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:558-562 [Conf]
  103. Hong Liu, Fung-Yuel Chang, Omar Wing
    Transient Analysis of VLSI Interconnects with Arbitrary Initial Distributions and Nonlinear Terminations. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:563-566 [Conf]
  104. Ali El-Zein, Monjurul Haque, S. Chowdhury
    Simulating Uniform Lossy Lines by the Time-Domain Modal Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:567-570 [Conf]
  105. Mehmet Emin Dalkiliç, Vijay Pitchumani
    A Multi-Schedule Approach to High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:572-575 [Conf]
  106. Alok Sharma, Rajiv Jain
    Register Estimation from Behavioral Specifications. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:576-580 [Conf]
  107. Thomas Charles Wilson, Gary William Grewal, Dilip K. Banerji
    An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:581-586 [Conf]
  108. Baher Haroun, Behzard Sajjadi
    Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:587-589 [Conf]
  109. Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai
    Optimal Design of Self-Damped Lossy Transmission Lines for Multichip Modules. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:594-598 [Conf]
  110. James Loy, Atul Garg, Mukkai S. Krishnamoorthy, John F. McDonald
    Differential Routing of MCMs - CIF: The Ideal Bifurcation Medium. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:599-603 [Conf]
  111. Mohammad Hossain Heydari, Ioannis G. Tollis, Chunliang Xia
    Improved Techniques for MCM Layer Assignment. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:604-607 [Conf]
  112. Atul Garg, T.-L. Sham, Hans J. Greub, James Loy, Jack F. McDonald
    Thermal Design of an Advanced Multichip Module for a RISC Processor. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:608-611 [Conf]
  113. Razak Hossain, Menghui Zheng, Alexander Albicki
    Reducing Power Dissipation in Serially Connected MOSFET Circuits via Transistor Reordering. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:614-617 [Conf]
  114. Horng-Dar Lin, Ran-Hong Yan, Douglas Yu
    Improving CMOS Speed at Low Supply Voltages. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:618-621 [Conf]
  115. Santanu Dutta, Wayne Wolf
    Asymptotic Limits of Video Signal Processing Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:622-625 [Conf]
  116. Hans Lindkvist, Per Andersson
    Techniques for Fast CMOS-based Conditional Sum Adders. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:626-635 [Conf]
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