Conferences in DBLP
Gianpiero Cabodi , Luciano Lavagno , Enrico Macii , Massimo Poncino , Stefano Quer , Paolo Camurati , Ellen Sentovich Enhancing FSM Traversal by Temporary Re-Encoding. [Citation Graph (0, 0)][DBLP ] Conf ] Ramin Hojati , Sriram C. Krishnan , Robert K. Brayton Early Quantification and Partitioned Transition Relations. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Langevin , Sofiène Tahar , Zijian Zhou , Xiaoyu Song , Eduard Cerny Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration. [Citation Graph (0, 0)][DBLP ] Conf ] Valeria Bertacco , Maurizio Damiani Boolean Function Representation Based on Disjoint-Support Decompositions. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios Kagaris , Spyros Tragoudas A multiseed counter TPG with performance guarantee. [Citation Graph (0, 0)][DBLP ] Conf ] Karim Arabi , Bozena Kaminska , Stephen K. Sunter Design for testability of integrated operational amplifiers using oscillation-test strategy. [Citation Graph (0, 0)][DBLP ] Conf ] Kamran Zarrineh , Vivek Chickermane , Gareth Nicholls , Mike Palmer A Design For Test Perspective on I/O Management. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh K. Gupta , Daniel Gajski , Randy Allen , Yatin Trivedi Opportunities and pitfalls in HDL-based system design. [Citation Graph (0, 0)][DBLP ] Conf ] Nian-Feng Tzeng , Steven Wallach Issues on the architecture and the design of distributed shared memory systems. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Lenoski Design issues for distributed shared-memory systems. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Wood , Mark D. Hill , James R. Larus The Tempest approach to distributed shared memory. [Citation Graph (0, 0)][DBLP ] Conf ] Pradeep Prabhakaran , Prithviraj Banerjee Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Mark C. Johnson , Kaushik Roy Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Yung-Ming Fang , D. F. Wong Multiplexor Network Generation in High Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] William O'Connell , Grace Au , David Schrader Multimodal query support in database servers. [Citation Graph (0, 0)][DBLP ] Conf ] W. Melody Moh , Yu-Feng Chung , Teng-Sheng Moh , Joanna Wang Evaluation of high speed LAN protocols as multimedia carriers . [Citation Graph (0, 0)][DBLP ] Conf ] David C. Chen , Bing J. Sheu , Theodore W. Berger A Compact Neural Network Based CDMA Receiver for Multimedia Wireless Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Yinan N. Shen , Nohpill Park , Fabrizio Lombardi Space Cutting Approaches for Repairing Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Orailoglu Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Y. Yun , Ryan P. Donohue Pausible Clocking: A First Step Toward Heterogeneous Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Walker , Sumit Ghosh On the Nature and Inadequacies of Transport Timing Delay Constructs in VHDL Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Albrecht P. Stroele Arithmetic Pattern Generators for Built-In Self-Test. [Citation Graph (0, 0)][DBLP ] Conf ] Naim Ben Hamida , Bechir Ayari , Bozena Kaminska Testing of embedded A/D converters in mixed-signal circuit. [Citation Graph (0, 0)][DBLP ] Conf ] N. Ranganathan , Narayanan Vijaykrishnan , N. Bhavanishankar A VLSI array architecture with dynamic frequency clocking. [Citation Graph (0, 0)][DBLP ] Conf ] Leon Alkalai , Wai-Chi Fang An integrated microspacecraft avionics architecture using 3D multichip module building blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Kozuch , Wayne Wolf , Andrew Wolfe New Challenges for Video Servers: Performance of Non-Linear Applications under User Choice. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Li An output-shared buffer ATM switch. [Citation Graph (0, 0)][DBLP ] Conf ] Chie Dou , Ming-Der Shieh A CAM-Based VLSI Architecture for Shared Buffer ATM Switch with Fuzzy Controlled Buffer Management. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Fault Location based on Circuit Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Maniatopoulos , Theodore Antonakopoulos , Vassilios Makios Design and Implementation of a new Synchronization Method for High-Speed Cell-based Network Interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] José Cruz-Rivera , D. Scott Wills , Thomas K. Gaylord , Elias N. Glytsis Modeling the Technology Impact on the Design of a Two-Level Multicomputer Interconnection Network. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios N. Serpanos , Leonidas Georgiadis , T. Bouloutas MMPacking: A Load and Storage Balancing Algorithm for Distributed Multimedia Servers. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Fu Memory Hierarchy Synthesis of a Multimedia Embedded Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Herrmann High Speed Video Board as a Case Study for Hardware-Software Co-Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Paul Theis , Lothar Thiele VLIW-Processors under Periodic Real Time Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] C. Alba , Luigi Carro , A. Lima , Altamiro Amadeu Susin Embedded Systems Design with Frontend Compilers. [Citation Graph (0, 0)][DBLP ] Conf ] Mamoru Sakamoto , Toyohiko Yoshida , Yasuhiro Nunomura , Yukihiko Shimazu Microarchitecture Support for Reducing Branch Penalty in a Supercscaler Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Pradeep K. Dubey , Ravi Nair Profile-Driven Generation of Trace Samples. [Citation Graph (0, 0)][DBLP ] Conf ] Yue Liu , David R. Kaeli Branch-Directed and Stride-Based Data Cache Prefetching. [Citation Graph (0, 0)][DBLP ] Conf ] Gyungho Lee , Bland Quattlebaum , Sangyeun Cho , Larry L. Kinney Global Bus Design of a Bus-Based COMA Multiprocessor DICE. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Fault Location Based on Circuit Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Li-C. Wang , M. Ray Mercer , Thomas W. Williams A Better ATPG Algorithm and Its Design Principles. [Citation Graph (0, 0)][DBLP ] Conf ] Jaehong Park , M. Ray Mercer Using Functional Information and Strategy Switching in Sequential ATPG. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas E. Marchok , Wojciech Maly Modeling the Difficulty of Sequential Automatic Test Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Steven P. Larcombe , David J. Prendergast , Neil A. Thacker , Peter A. Ivey Using Genetic Algorithms to Automate System Implementation in a Novel Three-Dimensional Packaging Technolog. [Citation Graph (0, 0)][DBLP ] Conf ] J. Kampe , C. Wisser , G. Scarbata Module Generators for a Regular Analog Layout. [Citation Graph (0, 0)][DBLP ] Conf ] Jose Alvarez , Hector Sanchez , Roger Countryman , Mike Alexander , Carmine Nicoletta , Gianfranco Gerosa A Scalable Resistor-less PLL Design for PowerPCTM Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Mauricio Breternitz Jr. , A. Manikonda , M. Ommerman , W. Su , A. Thornto Design Tradeoffs and Experience with Motorola PowerPC? Migration Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Philip Koopman Embedded System Design Issues (The Rest of the Story). [Citation Graph (0, 0)][DBLP ] Conf ] Soo-Young Oh , Khalid Rahmat , O. Sam Nakagawa , J. Moll A Scaling Scheme and Optimization Methodology for Deep Sub-Micron Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Fran Hancheck , Shantanu Dutt Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Gin Yee , Carl Sechen Clock-Delayed Domino for Adder and Combinational Logic Desig. [Citation Graph (0, 0)][DBLP ] Conf ] Richard J. Lipton DNA computations can have global memory. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Thiry , Luc J. M. Claesen A formal verification technique for embedded software. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev K. Ranjan , Jagesh V. Sanghavi , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Binary decision diagrams on network of workstation. [Citation Graph (0, 0)][DBLP ] Conf ] Prakash Arunachalam , Craig M. Chase , Dinos Moundanos Distributed Binary Decision Diagrams for Verification of Large Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Florian Krohm , Andreas Kuehlmann , Arjen Mets The use of random simulation in formal verification. [Citation Graph (0, 0)][DBLP ] Conf ] Bingzhong Guan , Carl Sechen Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Bevacqua , Luca Guerrazzi , Fabrizio Ferrandi , Franco Fummi Implicit Test Sequences Compaction for Decreasing Test Application Cos. [Citation Graph (0, 0)][DBLP ] Conf ] Lakshmikant Bhupathi , Liang-Fang Chao Dichotomy-based Model for FSM Power Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh Pendurkar , Abhijit Chatterjee , Craig A. Tovey Optimal single probe traversal algorithm for testing of MCM substrat. [Citation Graph (0, 0)][DBLP ] Conf ] Stas Polonsky RSFQ: What We Know and What We Don't. [Citation Graph (0, 0)][DBLP ] Conf ] Priyadarsan Patra , Donald S. Fussell Efficient Delay-Insensitive RSFQ Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshio Kameda Pulse-Driven Delay-Insensitive Circuits using Single-Flux-Quantum Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Coudert , C.-J. Richard Shi Exact Dichotomy-based Constrained Encodi. [Citation Graph (0, 0)][DBLP ] Conf ] Shaz Qadeer , Robert K. Brayton , Vigyan Singhal Latch Redundancy Removal Without Global Reset. [Citation Graph (0, 0)][DBLP ] Conf ] Naresh Maheshwari , Sachin S. Sapatnekar A Practical Algorithm for Retiming Level-Clocked Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Alessandro Bogliolo , Giovanni De Micheli Distributed EDA Tool Integration: The PPP Paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan G. Arsintescu A Method for Analog Circuits Visualization. [Citation Graph (0, 0)][DBLP ] Conf ] Kei-Yong Khoo , Alan N. Willson Jr. Cycle-Based Timing Simulations Using Event-Stream. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas M. Conte , Mary Ann Hirsch , Kishore N. Menezes Reducing State Loss For Effective Trace Sampling of Superscalar Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Bryan Black , Andrew S. Huang , Mikko H. Lipasti , John Paul Shen Can Trace-Driven Simulators Accurately Predict Superscalar Performance? [Citation Graph (0, 0)][DBLP ] Conf ] Anthony-Trung Nguyen , Maged M. Michael , Arun Sharma , Josep Torrellas The Augmint multiprocessor simulation toolkit for Intel x86 architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Janardhan H. Satyanarayana , Keshab K. Parhi , Leilei Song , Yun-Nan Chang Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] S. B. Aruru , N. Ranganathan , Kameswara Rao Namuduri A VLSI chip for image compression using variable block size segmentation. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Long Wey On Design of Efficient Square Generator. [Citation Graph (0, 0)][DBLP ] Conf ] H. Fatih Ugurdag , Thomas E. Fuhrman Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath. [Citation Graph (0, 0)][DBLP ] Conf ] Nelson L. Passos , Edwin Hsing-Mean Sha Synthesis of Multi-Dimensional Applications in VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Yamin Li , Wanming Chu A New Non-Restoring Square Root Algorithm and its VLSI Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] David R. Lutz , D. N. Jayasimha Early Zero Detection. [Citation Graph (0, 0)][DBLP ] Conf ] D. Kuguris , Spyros Tragoudas FPGA Module Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Chang Wu An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig. [Citation Graph (0, 0)][DBLP ] Conf ] Vijayanand Sankarasubramanian , Dinesh Bhatia Multiway Partitioner for High Performance FPGA Based Board Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] 