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Conferences in DBLP

International Conference on Computer Design (ICCD) (iccd)
2001 (conf/iccd/2001)

  1. Karl-Thomas Neumann
    The In-Car Computing Network: An Embedded Systems Challenge. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:3-3 [Conf]
  2. John Paul Shen
    Clear and Present Tensions in Microprocessor Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:4-4 [Conf]
  3. Lee Harrison
    Moore's Law Meets Shannon's Law: The Evolution of the Communication's Industry. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:5-8 [Conf]
  4. Montek Singh, Steven M. Nowick
    MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:9-17 [Conf]
  5. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
    Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:18-23 [Conf]
  6. Fu-Chiung Cheng, Shuen-Long Ho
    Efficient Systematic Error-correcting Codes for Semi-Delay-Insensitive Data Transmission. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:24-31 [Conf]
  7. John W. Haskins Jr., Kevin Skadron
    Minimal Subset Evaluation: Rapid Warm-Up for Simulated Hardware State. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:32-39 [Conf]
  8. Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    A Framework for Energy Estimation of VLIW Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:40-45 [Conf]
  9. Li Shang, Niraj K. Jha
    High-Level Power Modeling of CPLDs and FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:46-53 [Conf]
  10. Qianrong Ma, Jih-Kwon Peir, Lu Peng, Konrad Lai
    Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:54-61 [Conf]
  11. Aamer Jaleel, Bruce L. Jacob
    In-Line Interrupt Handling for Software-Managed TLBs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:62-67 [Conf]
  12. Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau
    Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:68-75 [Conf]
  13. Farzan Fallah, Koichiro Takayama
    A New Functional Test Program Generation Methodology. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:76-81 [Conf]
  14. Serdar Tasiran, Farzan Fallah, David G. Chinnery, Scott J. Weber, Kurt Keutzer
    A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:82-88 [Conf]
  15. Lee D. McFearin, David W. Matula
    Selecting A Well Distributed Hard Case Test Suite for IEEE Standard Floating Point Division. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:89-97 [Conf]
  16. Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee, Charlie Chung-Ping Chen
    Linear Time Hierarchical Capacitance Extraction without Multipole Expansion. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:98-103 [Conf]
  17. Payam Heydari, Massoud Pedram
    Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:104-109 [Conf]
  18. Masao Takahashi, Masanori Hashimoto, Hidetoshi Onodera
    Crosstalk Noise Estimation for Generic RC Trees. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:110-117 [Conf]
  19. Jung-Hoon Lee, Jang-Soo Lee, Seh-Woong Jeong, Shin-Dug Kim
    A Banked-Promotion TLB for High Performance and Low Power. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:118-123 [Conf]
  20. Wei-Fen Lin, Steven K. Reinhardt, Doug Burger, Thomas R. Puzak
    Filtering Superfluous Prefetches Using Density Vectors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:124-132 [Conf]
  21. Edward S. Tam, Stevan A. Vlaovic, Gary S. Tyson, Edward S. Davidson
    Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:133-141 [Conf]
  22. Irith Pomeranz, Sudhakar M. Reddy
    COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:142-147 [Conf]
  23. Irith Pomeranz, Sudhakar M. Reddy
    A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:148-153 [Conf]
  24. Dong Xiang, Yi Xu
    Cost-Effective Non-Scan Design for Testability for Actual Testability Improvement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:154-160 [Conf]
  25. Hagen Ploog, Sebastian Flügel, Dirk Timmermann
    Improved ZDN-arithmetic for Fast Modulo Multiplication. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:166-171 [Conf]
  26. Pablo I. Balzola, Michael J. Schulte, Jie Ruan, C. John Glossner, Erdem Hokenek
    Design Alternatives for Parallel Saturating Multioperand Adders. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:172-177 [Conf]
  27. Mark G. Arnold, Mark D. Winkel
    A Single-Multiplier Quadratic Interpolator for LNS Arithmetic. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:178-185 [Conf]
  28. Tong Xiao, Malgorzata Marek-Sadowska
    Gate Sizing to Eliminate Crosstalk Induced Timing Violation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:186-191 [Conf]
  29. Tai-Chen Chen, Song-Ra Pan, Yao-Wen Chang
    Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:192-198 [Conf]
  30. Shih-Yih Lai, Ross Baldick
    Buffered Interconnect Tree Optimization Using Lagrangian Relaxation and Dynamic Programming. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:199-207 [Conf]
  31. Payam Heydari, Massoud Pedram
    Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:209-213 [Conf]
  32. Martin Saint-Laurent, Madhavan Swaminathan, James D. Meindl
    On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:214-220 [Conf]
  33. Kenneth L. Shepard, Yu Zheng
    On-Chip Oscilloscopes for Noninvasive Time-domain Measurement of Waveforms. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:221-227 [Conf]
  34. Juan L. Aragón, José González, José M. García, Antonio González
    Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:228-233 [Conf]
  35. Yan Solihin, Kirk W. Cameron, Yong Luo, Dominique Lavenier, Maya Gokhale
    Mutable Functional Units and Their Applications on Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:234-239 [Conf]
  36. Qing Zhao, David J. Lilja
    Compiler-Directed Classification of Value Locality Behavior. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:240-248 [Conf]
  37. Vadhiraj Sankaranarayanan, Akhilesh Tyagi
    A Hierarchical Dependence Check and Folded Rename Mapping Based Scalable Dispatch Stage. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:249-255 [Conf]
  38. Georg Pelz
    Designing Circuits for Disk Drives. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:256-261 [Conf]
  39. James Jeppensen, Walt Allen, Steve Anderson, Michael Pilsl
    Hard Disk Controller: The Disk Drive's Brain and Body. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:262-267 [Conf]
  40. Wolfgang Sereinig
    Motion-Control: The Power Side of Disk Drives. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:268-275 [Conf]
  41. Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger
    Static Energy Reduction Techniques for Microprocessor Caches. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:276-283 [Conf]
  42. Deepak Limaye, Ryan Rakvic, John Paul Shen
    Parallel Cachelets. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:284-292 [Conf]
  43. Bhooshan S. Thakar, Gyungho Lee
    Access Region Cache: A Multi-Porting Solution for Future Wide-Issue Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:293-301 [Conf]
  44. Dragos Lungeanu, C.-J. Richard Shi
    Distributed Event-Driven Simulation of VHDL-SPICE Mixed-Signal Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:302-307 [Conf]
  45. Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller
    High Performance Parallel Fault Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:308-313 [Conf]
  46. Seongwoo Kim, Arun K. Somani
    On-Line Integrity Monitoring of Microprocessor Control Logic. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:314-321 [Conf]
  47. Fan Mo, Abdallah Tabbara, Robert K. Brayton
    A Timing-Driven Macro-Cell Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:322-327 [Conf]
  48. Saurabh N. Adya, Igor L. Markov
    Fixed-outline Floorplanning through Better Local Search. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:328-334 [Conf]
  49. Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang
    Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:335-347 [Conf]
  50. Katarzyna Radecka, Zeljko Zilic
    Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:348-353 [Conf]
  51. Christoph Meinel, Christian Stangier
    Hierarchical Image Computation with Dynamic Conjunction Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:354-359 [Conf]
  52. Jin Yang, Carl-Johan H. Seger
    Introduction to Generalized Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:360-367 [Conf]
  53. William N. N. Hung, Xiaoyu Song
    BDD Variable Ordering by Scatter Search. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:368-373 [Conf]
  54. Alicia Manthe, C.-J. Richard Shi
    Lower Bound Based DDD Minimization for Efficient Symbolic Circuit Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:374-379 [Conf]
  55. Laurie A. Smith King, Heather Quinn, Miriam Leeser, Demetris G. Galatopoullos, Elias S. Manolakos
    Run-Time Execution of Reconfigurable Hardware in a Java Environment. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:380-387 [Conf]
  56. Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura
    Realization of Multiple-Output Functions by Reconfigurable Cascades. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:388-393 [Conf]
  57. Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woong Jeong
    A Low-Power Cache Design for CalmRISCTM-Based Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:394-399 [Conf]
  58. Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl
    Interconnect-centric Array Architectures for Minimum SRAM Access Time. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:400-405 [Conf]
  59. Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
    Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:406-414 [Conf]
  60. Deependra Talla, Lizy Kurian John
    Cost-effective Hardware Acceleration of Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:415-424 [Conf]
  61. Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
    MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:425-430 [Conf]
  62. Markus Lorenz, Rainer Leupers, Peter Marwedel, Thorsten Dräger, Gerhard Fettweis
    Low-Energy DSP Code Generation Using a Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:431-437 [Conf]
  63. Ali Manzak, Chaitali Chakrabarti
    Voltage Scaling for Energy Minimization with QoS Constraints. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:438-446 [Conf]
  64. Ying Zhao, Sharad Malik, Albert Wang, Matthew W. Moskewicz, Conor F. Madigan
    Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:447-452 [Conf]
  65. John Patrick McGregor, Ruby B. Lee
    Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:453-461 [Conf]
  66. Hiroaki Kobayashi, Ken-ichi Suzuki, Kentaro Sano, Yoshiyuki Kaeriyama, Yasumasa Saida, Nobuyuki Oba, Tadao Nakamura
    3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:462-467 [Conf]
  67. Samarjeet Singh Tomar, Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
    Use of Local Memory for Efficient Java Execution. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:468-476 [Conf]
  68. Afzal Hossain, Daniel J. Pease
    An Analytical Model for Trace Cache Instruction Fetch Performance. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:477-480 [Conf]
  69. Jiang Hu, Sachin S. Sapatnekar
    Performance Driven Global Routing Through Gradual Refinement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:481-483 [Conf]
  70. Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aiman H. El-Maleh
    Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:484-487 [Conf]
  71. Felix Sheng-Ho Chang, Alan J. Hu
    Fast Specification of Cycle-accurate Processor Models. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:488-492 [Conf]
  72. Witawas Srisa-an, Chia-Tien Dan Lo, J. Morris Chang
    A Performance Analysis of the Active Memory System. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:493-496 [Conf]
  73. Kent E. Wires, Michael J. Schulte, James E. Stine
    Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:497-500 [Conf]
  74. Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
    An Algorithm for Dynamically Reconfigurable FPGA Placement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:501-504 [Conf]
  75. Pradeepsunder Ganesh, Charlie Chung-Ping Chen
    RC-in RC-out Model Order Reduction Accurate up to Second Order Moments. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:505-506 [Conf]
  76. James W. Hauser, Carla Neaderhouser Purdy
    Efficient Function Approximation for Embedded and ASIC Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:507-510 [Conf]
  77. Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park
    An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:511-512 [Conf]
  78. Hong-Sik Kim, Jin-kyue Lee, Sungho Kang
    A Heuristic for Multiple Weight Set Generation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:513-514 [Conf]
  79. Prosenjit Chatterjee, Ganesh Gopalakrishnan
    towards A formal Model of Shared Memory Consistency for Intel ItaniumTM. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:515-518 [Conf]
  80. Jennifer L. White, Moon-Jung Chung, Anthony S. Wojcik, Travis E. Doom
    Efficient Algorithms for Subcircuit Enumeration and Classification for the Module Identification Problem. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:519-522 [Conf]
  81. Halima El Naga, Jean-Luc Gaudiot
    MCOMA: A Multithreaded COMA Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:523-525 [Conf]
  82. Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar
    Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:526-529 [Conf]
  83. Pipat Reungsang, Sun Kyu Park, Seh-Woong Jeong, Hyung-Lae Roh, Gyungho Lee
    Reducing Cache Pollution of Prefetching in a Small Data Cache. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:530-533 [Conf]
  84. Rajesh Ramanujam, Murali Ravirala, Gyungho Lee
    Alloyed Path-pattern Scheme for Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:534-537 [Conf]
  85. Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija
    Timing Characterization of Dual-edge Triggered Flip-flops. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:538-541 [Conf]
  86. A. Murat Fiskiran, Ruby B. Lee
    Performance Impact of Addressing Modes on Encryption Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:542-545 [Conf]
  87. Noureddine Chabini, El Mostapha Aboulhamid, Yvon Savaria
    Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:546-552 [Conf]
  88. James D. Z. Ma, Arvind Parihar, Lei He
    Pre-routing Estimation of Shielding for RLC Signal Integrity. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:553-556 [Conf]
NOTICE1
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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