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International Conference on Computer Design (ICCD) (iccd)
2005 (conf/iccd/2005)


  1. Organizing Committee. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:- [Conf]

  2. Program Committee. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:- [Conf]

  3. Additional Reviewers. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:- [Conf]

  4. Welcome Message. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:- [Conf]

  5. Title Page. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:- [Conf]

  6. Copyright. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:- [Conf]
  7. David A. Patterson
    Latency Lags Bandwidth. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:3-6 [Conf]
  8. Peng Li, Yangdong Deng, Lawrence T. Pileggi
    Temperature-Dependent Optimization of Cache Leakage Power Dissipation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:7-12 [Conf]
  9. Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija
    Architectural Considerations for Energy Efficiency. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:13-16 [Conf]
  10. Anahita Shayesteh, Eren Kursun, Timothy Sherwood, Suleyman Sair, Glenn Reinman
    Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:17-23 [Conf]
  11. Kyeong-Jae Lee, Kevin Skadron, Wei Huang
    Analytical Model for Sensor Placement on Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:24-30 [Conf]
  12. Qinghua Liu, Malgorzata Marek-Sadowska
    Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:31-37 [Conf]
  13. Zion Cien Shen, Chris C. N. Chu, Ying-Meng Li
    Efficient Rectilinear Steiner Tree Construction with Rectilinear Blockages. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:38-44 [Conf]
  14. Seraj Ahmad, Nikhil Jayakumar, Vijay Balasubramanian, Edward Hursey, Sunil P. Khatri, Rabi N. Mahapatra
    X-Routing using Two Manhattan Route Instances. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:45-52 [Conf]
  15. Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. Bhuyan, Donald Newell
    Hardware Support for Bulk Data Movement in Server Platforms. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:53-60 [Conf]
  16. Mazen Kharbutli, Yan Solihin
    Counter-Based Cache Replacement Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:61-68 [Conf]
  17. Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski
    Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:69-76 [Conf]
  18. Rich Faris, Ken Larsen, Harry Foster, Stuart Swan
    Are Today's Verification Tools Able to Handle Current Design Challenges? [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:77- [Conf]
  19. Andi Nourrachmat, Sabino Salerno, Enrico Macii, Massimo Poncino
    Energy-Efficient Color Approximation for Digital LCD Interfaces. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:81-86 [Conf]
  20. Martino Ruggiero, Andrea Acquaviva, Davide Bertozzi, Luca Benini
    Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:87-93 [Conf]
  21. Vasily G. Moshnyaga, Eiji Morikawa
    LCD Display Energy Reduction by User Monitoring. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:94-97 [Conf]
  22. Kimish Patel, Enrico Macii, Massimo Poncino
    Frame Buffer Energy Optimization by Pixel Prediction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:98-101 [Conf]
  23. Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede
    Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor System. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:102-104 [Conf]
  24. Nevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem
    Near-memory Caching for Improved Energy Consumption. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:105-110 [Conf]
  25. Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng
    Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:111-118 [Conf]
  26. Shrirang M. Yardi, Karthik Channakeshava, Michael S. Hsiao, Thomas L. Martin, Dong S. Ha
    A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:119-126 [Conf]
  27. Soheil Ghiasi
    Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case Study. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:127-129 [Conf]
  28. Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang
    Efficient Thermal Simulation for Run-Time Temperature Tracking and Management. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:130-136 [Conf]
  29. Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
    A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:137-142 [Conf]
  30. Gang Zeng, Hideo Ito
    Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:143-146 [Conf]
  31. Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
    ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:147-152 [Conf]
  32. Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng
    Accurate Diagnosis of Multiple Faults. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:153-156 [Conf]
  33. Jheng-Syun Yang, Shi-Yu Huang
    Quick Scan Chain Diagnosis Using Signal Profiling. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:157-160 [Conf]
  34. Fang Liu, Sule Ozev
    Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:161-170 [Conf]
  35. Song Peng, Rajit Manohar
    Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:171-179 [Conf]
  36. Lei Wang
    Error-tolerance memory Microarchitecture via Dynamic Multithreading. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:179-184 [Conf]
  37. Patrick Ndai, Amit Agarwal, Qikai Chen, Kaushik Roy
    A Soft Error Monitor Using Switching Current Detection. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:185-192 [Conf]
  38. Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler
    Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:193-199 [Conf]
  39. Koji Ohashi, Mineo Kaneko
    Statistical Analysis Driven Synthesis of Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:200-205 [Conf]
  40. Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy
    Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:206-214 [Conf]
  41. Namrata Shekhar, Priyank Kalla, Sivaram Gopalakrishnan, Florian Enescu
    Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic Datapaths. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:215-220 [Conf]
  42. Marc Boule, Zeljko Zilic
    Incorporating Ef.cient Assertion Checkers into Hardware Emulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:221-228 [Conf]
  43. Iñigo Ugarte, Pablo Sanchez
    Assertion Checking of Behavioral Descriptions with Non-linear Solver. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:229-231 [Conf]
  44. Bhanu Pisupati, Geoffrey Brown
    File System Interfaces for Embedded Software Development. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:232-238 [Conf]
  45. Michael J. Flynn
    Yesterday and Tomorrow: A View on Progress in Computer Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:239-242 [Conf]
  46. Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara
    Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:243-248 [Conf]
  47. Milena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija
    Low- and Ultra Low-Power Arithmetic Units: Design and Comparison. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:249-252 [Conf]
  48. Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail
    A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:253-257 [Conf]
  49. Tetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Oguray, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori
    Low-Power Design of 90-nm SuperH Processor Core. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:258-266 [Conf]
  50. Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton
    Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:267-274 [Conf]
  51. Aswin C. Sankaranarayanan, Rama Chellappa, Ankur Srivastava
    Algorithmic and Architectural Design Methodology for Particle Filters in Hardware. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:275-280 [Conf]
  52. Wei Zhang, Niraj K. Jha
    ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:281-288 [Conf]
  53. Li-Kai Chang, Fu-Chiung Cheng
    Automatic Synthesis of Composable Sequential Quantum Boolean Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:289-296 [Conf]
  54. Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Malay K. Ganai
    Model Checking C Programs Using F-SOFT. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:297-308 [Conf]
  55. Mark A. Hillebrand, Thomas In der Rieden, Wolfgang J. Paul
    Dealing with I/O Devices in the Context of Pervasive System Verification. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:309-316 [Conf]
  56. Sven Beyer, Peter Böhm, Michael Gerke 0002, Mark A. Hillebrand, Thomas In der Rieden, Steffen Knapp, Dirk Leinenbach, Wolfgang J. Paul
    Towards the Formal Verification of Lower System Layers in Automotive Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:317-326 [Conf]
  57. Prateek Pujara, Aneesh Aggarwal
    Restrictive Compression Techniques to Increase Level 1 Cache Capacity. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:327-333 [Conf]
  58. Jan-Willem van de Waerdt, Stamatis Vassiliadis, Jean-Paul van Itegem, Hans Van Antwerpen
    The TM3270 Media-Processor Data Cache. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:334-341 [Conf]
  59. Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
    Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:342-350 [Conf]
  60. Soroush Abbaspour, Hanif Fatemi, Massoud Pedram
    VGTA: Variation Aware Gate Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:351-356 [Conf]
  61. Felipe R. Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis
    Exact lower bound for the number of switches in series to implement a combinational logic cell. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:357-362 [Conf]
  62. Peng Li, Emrah Acar
    A Waveform Independent Gate Model for Accurate Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:363-365 [Conf]
  63. Fei Hu, Vishwani D. Agrawal
    Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:366-372 [Conf]
  64. Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Daniel A. Connors
    Methods for Modeling Resource Contention on Simultaneous Multithreading Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:373-380 [Conf]
  65. Carl S. Lebsack, J. Morris Chang
    Using Scratchpad to Exploit Object Locality in Java. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:381-386 [Conf]
  66. Khaled Z. Ibrahim
    Correlation between Detailed and Simplified Simulations in Studying Multiprocessor Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:387-392 [Conf]
  67. Yue Luo, Lizy Kurian John
    Simulating Commercial Java Throughput Workloads: A Case Study. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:393-398 [Conf]
  68. Nikhil Jayakumar, Sunil P. Khatri
    Minimum Energy Near-threshold Network of PLA based Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:399-404 [Conf]
  69. Jinhui Chen, Lawrence T. Clark, Yu Cao
    Robust Design of High Fan-In/Out Subthreshold Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:405-410 [Conf]
  70. Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee
    A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:411-416 [Conf]
  71. Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy
    A Feasibility Study of Subthreshold SRAM Across Technology Generations. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:417-424 [Conf]
  72. Azadeh Davoodi, Ankur Srivastava
    Variability-Driven Buffer Insertion Considering Correlations. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:425-430 [Conf]
  73. Valmiki Mukherjee, Saraju P. Mohanty, Elias Kougianos
    A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:431-437 [Conf]
  74. Andrew B. Kahng, Bao Liu, Qinke Wang
    Supply Voltage Degradation Aware Analytical Placement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:437-443 [Conf]
  75. Anuradha Agarwal, Ranga Vemuri
    Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:444-452 [Conf]
  76. Manan Syal, Rajat Arora, Michael S. Hsiao
    Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:453-460 [Conf]
  77. Qiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham
    Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:461-463 [Conf]
  78. Maria K. Michael, Kyriakos Christou, Spyros Tragoudas
    Towards finding path delay fault tests with high test efficiency using ZBDDs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:464-467 [Conf]
  79. M. M. Vaseekar Kumar, Spyros Tragoudas
    Quality Transition Fault Tests Suitable for Small Delay Defects. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:468-470 [Conf]
  80. N. Devtaprasanna, A. Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
    A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:471-474 [Conf]
  81. Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo
    At-Speed Logic BIST Architecture for Multi-Clock Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:475-478 [Conf]
  82. Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng
    Hardware Ef.cient LBISTWith Complementary Weights. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:479-484 [Conf]
  83. Rick Bailey, Glen Fox, Jarrod Eliason, Marty Depner, Daesig Kim, Edwin Jabillo, John Groat, John Walbert, Scott Summerfelt, K. R. Udayakumar, John Rodriquez, Keith Remack, K. Boku, John Gertas
    FRAM Memory Technology - Advantages for Low Power, Fast Write, High Endurance Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:485- [Conf]
  84. Hua Li, Jianzhou Li
    A High Performance Sub-Pipelined Architecture for AES. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:491-496 [Conf]
  85. Hongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris
    Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:497-502 [Conf]
  86. Kazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa
    Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:503-510 [Conf]
  87. Anatoly I. Grushin
    Fast Minimum and Maximum Selection. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:511-518 [Conf]
  88. Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    Three-Dimensional Cache Design Exploration Using 3DCacti. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:519-524 [Conf]
  89. Kiran Puttaswamy, Gabriel H. Loh
    Implementing Caches in a 3D Technology for High Performance Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:525-532 [Conf]
  90. Wenjing Rao, Alex Orailoglu, Ramesh Karri
    Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:533-542 [Conf]
  91. Milo M. K. Martin
    Formal Verification and its Impact on the Snooping versus Directory Protocol Debate. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:543-449 [Conf]
  92. Todd M. Austin, Valeria Bertacco
    Deployment of Better Than Worst-Case Design: Solutions and Needs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:550-558 [Conf]
  93. Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif
    Benefits and Costs of Power-Gating Technique. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:559-566 [Conf]
  94. Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De
    A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:567-573 [Conf]
  95. Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, J. C. Law, Rajiv V. Joshi
    A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:574-584 [Conf]
  96. Kameshwar Chandrasekar, Michael S. Hsiao
    State Set Management for SAT-based Unbounded Model Checking. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:585-590 [Conf]
  97. Anubhav Gupta, Edmund M. Clarke
    Reconsidering CEGAR: Learning Good Abstractions without Refinement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:591-598 [Conf]
  98. Nikhil Kikkeri, Peter-Michael Seidel
    Formal Verification of Parametric Multiplicative Division Implementations. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:599-602 [Conf]
  99. Nathaniel Ayewah, Nikhil Kikkeri, Peter-Michael Seidel
    Challenges in the Formal Verification of Complete State-of-the-Art Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:603-608 [Conf]
  100. Won-Ho Park, Andreas Moshovos, Babak Falsafi
    RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free". [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:609-616 [Conf]
  101. Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang
    Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism.. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:617-624 [Conf]
  102. Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras
    Optimizing the Thermal Behavior of Subarrayed Data Caches. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:625-630 [Conf]
  103. Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang
    VALVE: Variable Length Value Encoder for Off-Chip Data Buses.. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:631-633 [Conf]
  104. Sivakumar Velusamy, Wei Huang, John Lach, Mircea R. Stan, Kevin Skadron
    Monitoring Temperature in FPGA based SoCs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:634-640 [Conf]
  105. Yongxiang Liu, Gokhan Memik, Glenn Reinman
    Reducing the Energy of Speculative Instruction Schedulers. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:641-646 [Conf]
  106. Marco A. Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa
    A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:647-653 [Conf]
  107. Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin
    Power-Efficient Wakeup Tag Broadcast. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:654-661 [Conf]
  108. Rania Mameesh, Manoh Franklin
    SST: Symbolic Subordinate Threading. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:662-665 [Conf]
  109. Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio González
    Memory Bank Predictors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:666-670 [Conf]
  110. Xizhen Xu, Sotirios G. Ziavras
    H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:671-676 [Conf]
  111. Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T. Kandemir, Yuan Xie
    Temperature-Sensitive Loop Parallelization for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:677-682 [Conf]
  112. Brock J. LaMeres, Sunil P. Khatri
    Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:683-688 [Conf]
  113. Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwad, John Conner
    Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:689-696 [Conf]
  114. Nathan Kitchen, Andreas Kuehlmann
    Temporal Decomposition for Logic Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:697-702 [Conf]
  115. Luis A. Plana, Sam Taylor, Doug Edwards
    Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:703-710 [Conf]
  116. Yung-Chih Chen, Chun-Yao Wang
    An Improved Approach for AlternativeWires Identi.cation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:711-716 [Conf]
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