Conferences in DBLP
Justin R. Rattner Supercomputing on a Chip: Evolution and Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrich Ramacher Application Specific Embedded Processors for Next Generation Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Raul Camposano From IP to Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Mizuno , Kazuyoshi Kohno , Ryuichiro Ohyama , Takahiro Tokuyoshi , Hironori Uetani , Hans Eichel , Takashi Miyamori , Nobu Matsumoto , Masataka Matsui Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Ralf Kakerow Low Power Design Methodologies for Mobile Communication. [Citation Graph (0, 0)][DBLP ] Conf ] H. Peter Hofstee Power-Constrained Microprocessor Design. [Citation Graph (0, 0)][DBLP ] Conf ] Joerg Walter Functional Verification of the IBM zSeries eServer z900 System. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Seok (Andy) Seo , Abhijit Chatterjee A CAD Tool for System-on-Chip Placement and Routing with Free-Space Optical Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Hongyu Chen , Bo Yao , Feng Zhou , Chung-Kuan Cheng Physical Planning Of On-Chip Interconnect Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Stan Y. Liao , Narendra V. Shenoy , William Nicholls An Efficient External-Memory Implementation of Region Query with Application to Area Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Chang-Tzu Lin , De-Sheng Chen , Yi-Wen Wang GPE: A New Representation for VLSI Floorplan Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaojian Yang , Bo-Kyung Choi , Majid Sarrafzadeh A Standard-Cell Placement Tool for Designs with High Row Utilization. [Citation Graph (0, 0)][DBLP ] Conf ] Partha S. Roop , Arcot Sowmya , S. Ramesh k-time Forced Simulation: A Formal Verification Technique for IP Reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Christoph Scholl , Bernd Becker Checking Equivalence for Circuits Containing Incompletely Specified Boxes. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi A. Aloul , Igor L. Markov , Karem A. Sakallah Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering. [Citation Graph (0, 0)][DBLP ] Conf ] Hong Peng , Yassine Mokhtari , Sofiène Tahar Environment Synthesis for Compositional Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Groeneveld Physical Design Challenges for Billion Transistor Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt Keutzer , Sharad Malik , A. Richard Newton From ASIC to ASIP: The Next Design Discontinuity. [Citation Graph (0, 0)][DBLP ] Conf ] Surrendra Dudani , Jayant Nagda High Level Functional Verification Closure. [Citation Graph (0, 0)][DBLP ] Conf ] Sumio Morioka , Akashi Satoh A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Taubin , Karl Fant , John McCardle Design of Delay-Insensitive Three Dimension Pipeline Array Multiplier for Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo A. C. da Costa , Sergio Bampi , José Monteiro A New Architecture for Signed Radix-2m Pure Array Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Oguz Ergin , Kanad Ghose , Gurhan Kucuk , Dmitry Ponomarev A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Tyler Thorp , Dean Liu Analysis of Blocking Dynamic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jari Nikara , Stamatis Vassiliadis , Jarmo Takala , Mihai Sima , Petri Liuha Parallel Multiple-Symbol Variable-Length Decoding. [Citation Graph (0, 0)][DBLP ] Conf ] José-Alejandro Piñeiro , Milos D. Ercegovac , Javier D. Bruguera Analysis of the Tradeoffs for the Implementation of a High-Radix Logarithm. [Citation Graph (0, 0)][DBLP ] Conf ] Huesung Kim , Arun K. Somani , Akhilesh Tyagi Adaptive Balanced Computing (ABC) Microprocessor Using Reconfigurable Functional Caches (RFCs). [Citation Graph (0, 0)][DBLP ] Conf ] Tomás Lang , Javier D. Bruguera Floating-Point Fused Multiply-Add with Reduced Latency. [Citation Graph (0, 0)][DBLP ] Conf ] Louis Scheffer Methodologies and Tools for Pipelined On-Chip Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Rita Yu Chen , Paul Yip , Georgios Konstadinidis , Andrew Demas , Fabian Klass , Rob Mains , Margaret Schmitt , Dina Bistry Timing Window Applications in UltraSPARC-IIIi? Microprocessor Design. [Citation Graph (0, 0)][DBLP ] Conf ] B. Chappell , X. Wang , P. Patra , Prashant Saxena , J. Vendrell , Satyanarayan Gupta , S. Varadarajan , W. Gomes , S. Hussain , H. Krishnamurthy , M. Venkateshmurthy , S. Jain A System-Level Solution to Domino Synthesis with 2 GHz Application. [Citation Graph (0, 0)][DBLP ] Conf ] Hongbo Yang , Ramaswamy Govindarajan , Guang R. Gao , Kevin B. Theobald Power-Performance Trade-Offs for Energy-Efficient Architectures: A Quantitative Study. [Citation Graph (0, 0)][DBLP ] Conf ] Esther Y. Cheng , Feng Zhou , Bo Yao , Chung-Kuan Cheng , Ronald L. Graham Balancing the Interconnect Topology for Arrays of Processors between Cost and Power. [Citation Graph (0, 0)][DBLP ] Conf ] Koji Inoue , Vasily G. Moshnyaga , Kazuaki Murakami A Low Energy Set-Associative I-Cache with Extended BTB. [Citation Graph (0, 0)][DBLP ] Conf ] Kohei Miyase , Seiji Kajihara , Irith Pomeranz , Sudhakar M. Reddy Don't-Care Identification on Specific Bits of Test Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Michiko Inoue , Chikateru Jinno , Hideo Fujiwara An Extended Class of Sequential Circuits with Combinational Test Generation Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Galke , Matthias Pflanz , Heinrich Theodor Vierhaus A Test Processor Concept for Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Lewis Girod , Vladimir Bychkovskiy , Jeremy Elson , Deborah Estrin Locating Tiny Sensors in Time and Space: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Savvides , Mani B. Srivastava A Distributed Computation Platform for Wireless Embedded Sensing. [Citation Graph (0, 0)][DBLP ] Conf ] Jessica Feng , Farinaz Koushanfar , Miodrag Potkonjak System-Architectures for Sensor Networks Issues, Alternatives, and Directions. [Citation Graph (0, 0)][DBLP ] Conf ] Zhijie Shi , Ruby B. Lee Subword Sorting with Versatile Permutation Instructions. [Citation Graph (0, 0)][DBLP ] Conf ] Murali Annavaram , Trung A. Diep , John Paul Shen Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Witawas Srisa-an , Chia-Tien Dan Lo , J. Morris Chang Performance Enhancements to the Active Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] Sule Ozev , Alex Orailoglu Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] I-De Huang , Sandeep K. Gupta , Melvin A. Breuer Accurate and Efficient Static Timing Analysis with Crosstalk. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir , Zhen Guo On the Detectability of Parametric Faults in Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Steininger , Johann Vilanek Using Offline and Online BIST to Improve System Dependability - The TTPC-C Example. [Citation Graph (0, 0)][DBLP ] Conf ] Ujval J. Kapasi , William J. Dally , Scott Rixner , John D. Owens , Brucek Khailany The Imagine Stream Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Brucek Khailany , William J. Dally , Andrew Chang , Ujval J. Kapasi , Jinyung Namkoong , Brian Towles VLSI Design and Verification of the Imagine Processor. [Citation Graph (0, 0)][DBLP ] Conf ] John D. Owens , Scott Rixner , Ujval J. Kapasi , Peter R. Mattson , Brian Towles , Ben Serebrin , William J. Dally Media Processing Applications on the Imagine Stream Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Ben Serebrin , John D. Owens , Chen H. Chen , Stephen P. Crago , Ujval J. Kapasi , Peter R. Mattson , Jinyung Namkoong , Scott Rixner , William J. Dally A Stream Processor Development Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Tadahiro Kuroda Low-Power, High-Speed CMOS VLSI Design. [Citation Graph (0, 0)][DBLP ] Conf ] Stephanie Augsburger , Borivoje Nikolic Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Geun Rae Cho , Tom Chen On The Impact of Technology Scaling On Mixed PTL/Static Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Shanq-Jang Ruan , Edwin Naroska , Chia-Lin Ho , Feipei Lai Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yen-Jen Chang , Feipei Lai , Shanq-Jang Ruan Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost. [Citation Graph (0, 0)][DBLP ] Conf ] Jinwoo Kim , Krishna V. Palem , Weng-Fai Wong A Framework for Data Prefetching Using Off-Line Training of Markovian Predictors. [Citation Graph (0, 0)][DBLP ] Conf ] Afzal Hossain , Daniel J. Pease , James S. Burns , Nasima Parveen Trace Cache Performance Parameters. [Citation Graph (0, 0)][DBLP ] Conf ] Terry Lyon , Eric DeLano , Cameron McNairy , Dean Mulla Data Cache Design Considerations for the Itanium® 2 Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Joachim Schlosser Requirements for Automotive System Engineering Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Giusto , Jean-Yves Brunel , Alberto Ferrari , Eliane Fourgeau , Luciano Lavagno , Alberto L. Sangiovanni-Vincentelli Automotive Virtual Integration Platforms: Why's, What's, and How's. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Giusto , Jean-Yves Brunel , Alberto Ferrari , Eliane Fourgeau , Luciano Lavagno , Barry O'Rourke , Alberto L. Sangiovanni-Vincentelli , Emanuele Guasto Models of IP's for Automotive Virtual Integration Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] David Duarte , Narayanan Vijaykrishnan , Mary Jane Irwin , Hyun Suk Kim , G. McFarland Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjukta Bhanja , N. Ranganathan Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. [Citation Graph (0, 0)][DBLP ] Conf ] Lin Zhong , Jiong Luo , Yunsi Fei , Niraj K. Jha Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. [Citation Graph (0, 0)][DBLP ] Conf ] Seda Ogrenci Memik , Farzan Fallah Accelerated SAT-based Scheduling of Control/Data Flow Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Molina , Antonio González , Jordi Tubella Trace-Level Speculative Multithreaded Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Manvi Agarwal , S. K. Nandy , Jos T. J. van Eijndhoven , S. Balakrishnan Speculative Trace Scheduling in VLIW Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Tomas Henriksson , Ulf Nordqvist , Dake Liu Embedded Protocol Processor for Fast and Efficient Packet Reception. [Citation Graph (0, 0)][DBLP ] Conf ] Arif Ishaq Abou-Seido , Brian Nowak , Chris C. N. Chu Fitted Elmore Delay: A Simple and Accurate Interconnect Delay Model. [Citation Graph (0, 0)][DBLP ] Conf ] Guoan Zhong , Cheng-Kok Koh Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Haitian Hu , Sachin S. Sapatnekar Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Zhigang Hu , Philo Juang , Kevin Skadron , Douglas W. Clark , Margaret Martonosi Applying Decay Strategies to Branch Predictors for Leakage Energy Savings. [Citation Graph (0, 0)][DBLP ] Conf ] Ann Gordon-Ross , Frank Vahid Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Manfred Ley , Herbert Grünbacher TTA-C2, A Single Chip Communication Controller for the Time-Triggered-Protocol. [Citation Graph (0, 0)][DBLP ] Conf ] Aristides Efthymiou , Jim D. Garside Adaptive Pipeline Depth Control for Processor Power-Management. [Citation Graph (0, 0)][DBLP ] Conf ] Amirali Baniasadi , Andreas Moshovos Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Joshua J. Yi , David J. Lilja Improving Processor Performance by Simplifying and Bypassing Trivial Computations. [Citation Graph (0, 0)][DBLP ] Conf ] Nadir Z. Basturkmen , Sudhakar M. Reddy , Irith Pomeranz A Low Power Pseudo-Random BIST Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Paul M. Rosinger , Bashir M. Al-Hashimi , Nicola Nicolici Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding. [Citation Graph (0, 0)][DBLP ] Conf ] Baris Arslan , Alex Orailoglu Fault Dictionary Size Reduction through Test Response Superposition. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan Blunno , Luciano Lavagno Designing an Asynchronous Microcontroller Using Pipefitter. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Davide Bertozzi , Davide Bruni , Nicola Drago , Franco Fummi , Massimo Poncino Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Ihmor , Markus Visarius , Wolfram Hardt A Design Methodology for Application-Specific Real-Time Interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Stevan A. Vlaovic , Edward S. Davidson TAXI: Trace Analysis for X86 Interpretation. [Citation Graph (0, 0)][DBLP ] Conf ] Tat Kee Tan , Anand Raghunathan , Niraj K. Jha Embedded Operating System Energy Analysis and Macro-Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Domenico Barretta , William Fornaciari , Mariagiovanna Sami , Danilo Pau SIMD Extension to VLIW Multicluster Processors for Embedded Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Panit Watcharawitch , Simon W. Moore JMA: The Java-Multithreading Architecture for Embedded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] 