Conferences in DBLP
Mark Horowitz High-Speed Link Design, Then and Now. [Citation Graph (0, 0)][DBLP ] Conf ] William R. Pulleyblank Terascale Computing and BlueGene. [Citation Graph (0, 0)][DBLP ] Conf ] Ted Vucurevich Advanced EDA Tools for High-Performance Design. [Citation Graph (0, 0)][DBLP ] Conf ] Aneesh Aggarwal , Manoj Franklin Energy Efficient Asymmetrically Ported Register Files. [Citation Graph (0, 0)][DBLP ] Conf ] Jaume Abella , Antonio González Power Efficient Data Cache Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Jaume Abella , Antonio González On Reducing Register Pressure and Energy in Multiple-Banked Register Files. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Ito , David G. Chinnery , Kurt Keutzer Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Hao Zheng , Chris J. Myers , David Walter , Scott Little , Tomohiro Yoneda Verification of Timed Circuits with Failure Directed Abstractions. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Chen , Sudhakar M. Reddy , Irith Pomeranz Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Marong Phadoongsidhi , Kewal K. Saluja Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Edmund M. Clarke , Daniel Kroening , Karen Yorav Specifying and Verifying Systems with Multiple Clocks. [Citation Graph (0, 0)][DBLP ] Conf ] Wenjian Yu , Zeyi Wang , Xianlong Hong Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Liang Huang , Aurobindo Dasgupta An Improved method for Fast Noise Estimation based on Net Segmentation. [Citation Graph (0, 0)][DBLP ] Conf ] Hui-Yuan Song , S. Bohidar , R. Iris Bahar , Joel Grodstein Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. [Citation Graph (0, 0)][DBLP ] Conf ] Venkatesan Rajappan , Sachin S. Sapatnekar An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk. [Citation Graph (0, 0)][DBLP ] Conf ] Payman Zarkesh-Ha , Ken Doniger , William Loh , Dechang Sun , Rick Stephani , Gordon Priebe A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors. [Citation Graph (0, 0)][DBLP ] Conf ] Afshin Abdollahi , Massoud Pedram , Farzan Fallah , Indradeep Ghosh Precomputation-based Guarding for Dynamic and Leakage Power Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Saravanan Rajapandian , Zheng Xu , Kenneth L. Shepard Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Suzuki , Woopyo Jeong , Kaushik Roy Low Power Adder with Adaptive Supply Voltage. [Citation Graph (0, 0)][DBLP ] Conf ] Nestoras Tzartzanis , William W. Walker A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File. [Citation Graph (0, 0)][DBLP ] Conf ] Rastislav Levicky Detection of Biological Molecules: From Self-Assembled Films to Self-Integrated Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Ion I. Mandoiu , Sherief Reda , Xu Xu , Alexander Zelikovsky Design Flow Enhancements for DNA Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Nattawut Thepayasuwan , Vaishali Damle , Alex Doboli Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Vikas Chandra , Gary D. Carpenter , Jeff Burns Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Manev Luthra , Sumit Gupta , Nikil D. Dutt , Rajesh K. Gupta , Alexandru Nicolau Interface Synthesis using Memory Mapping for an FPGA Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Pinto , Luca P. Carloni , Alberto L. Sangiovanni-Vincentelli Efficient Synthesis of Networks On Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Reshadi , Nikil D. Dutt Reducing Compilation Time Overhead in Compiled Simulators. [Citation Graph (0, 0)][DBLP ] Conf ] Branden J. Moore , Thomas Slabach , Lambert Schaelicke Profiling Interrupt Handler Performance through Kernel Instrumentation. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna Kant , Ravishankar K. Iyer Design and Performance of Compressed Interconnects for High Performance Servers. [Citation Graph (0, 0)][DBLP ] Conf ] Karthikeyan Sankaralingam , Vincent Ajay Singh , Stephen W. Keckler , Doug Burger Routed Inter-ALU Networks for ILP Scalability and Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Joel Grodstein , Dilip K. Bhavsar , Vijay Bettada , Richard Davies Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Loganathan Lingappan , Srivaths Ravi , Niraj K. Jha Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Sobeeh Almukhaizim , Thomas Verdel , Yiorgos Makris Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyuan Wang , Malgorzata Marek-Sadowska , Kun-Han Tsai , Janusz Rajski Multiple Fault Diagnosis Using n-Detection Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Noriyuki Ito , Hiroaki Komatsu , Yoshiyasu Tanamura , Ryoichi Yamashita , Hiroyuki Sugiyama , Yaroku Sugiyama , Hirofumi Hamamura A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Yangdong Deng , Wojciech Maly Physical Design of the "2.5D" Stacked System. [Citation Graph (0, 0)][DBLP ] Conf ] Bo-Kyung Choi , Huaiyu Xu , Maogang Wang , Majid Sarrafzadeh Flow-Based Cell Moving Algorithm for Desired Cell Distribution. [Citation Graph (0, 0)][DBLP ] Conf ] Byeong Kil Lee , Lizy Kurian John NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Nihar R. Mahapatra , Jiangjiang Liu , Krishnan Sundaresan Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Guy Even , Peter-Michael Seidel Pipelined Multiplicative Division with IEEE Rounding. [Citation Graph (0, 0)][DBLP ] Conf ] Steven C. Chan , Kenneth L. Shepard , Phillip Restle Design of Resonant Global Clock Distributions. [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Balamurugan , Naresh R. Shanbhag Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Eckerbert , Lars J. Svensson , Per Larsson-Edefors A Mixed-Mode Delay-Locked-Loop Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Shidhartha Das , Kanak Agarwal , David Blaauw , Dennis Sylvester Optimal Inductance for On-chip RLC Interconnections. [Citation Graph (0, 0)][DBLP ] Conf ] Nataraj Akkiraju , Mosur Mohan Spec Based Flip-Flop And Buffer Insertion. [Citation Graph (0, 0)][DBLP ] Conf ] N. Ranganathan , Ashok K. Murugavel A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Rishi Chaturvedi , Jiang Hu A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chang Lai , Shih-Lien Lu Hardware-based Pointer Data Prefetcher. [Citation Graph (0, 0)][DBLP ] Conf ] Sriram Nadathur , Akhilesh Tyagi A Dependence Driven Efficient Dispatch Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Tay-Jyi Lin , Chin-Chi Chang , Chen-Chia Lee , Chein-Wei Jen An Efficient VLIW DSP Architecture for Baseband Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed M. Zahran , Manoj Franklin Dynamic Thread Resizing for Speculative Multithreaded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Könemann Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities. [Citation Graph (0, 0)][DBLP ] Conf ] Subhasish Mitra , Kee Sup Kim XMAX: X-Tolerant Architecture for MAXimal Test Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rajski , Jerzy Tyszer Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Aiqun Cao , Cheng-Kok Koh Non-Crossing OBDDs for Mapping to Regular Circuit Structures. [Citation Graph (0, 0)][DBLP ] Conf ] PariVallal Kannan , Dinesh Bhatia Interconnect Estimation for FPGAs under Timing Driven Domains. [Citation Graph (0, 0)][DBLP ] Conf ] Hasan Arslan , Shantanu Dutt ROAD : An Order-Impervious Optimal Detailed Router for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Victor Delaluz , Mahmut T. Kandemir , Anand Sivasubramaniam , Mary Jane Irwin , Narayanan Vijaykrishnan Reducing dTLB Energy Through Dynamic Resizing. [Citation Graph (0, 0)][DBLP ] Conf ] Gurhan Kucuk , Oguz Ergin , Dmitry Ponomarev , Kanad Ghose Distributed Reorder Buffer Schemes for Low Power. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Petrov , Alex Orailoglu Virtual Page Tag Reduction for Low-power TLBs. [Citation Graph (0, 0)][DBLP ] Conf ] José González , Antonio González Dynamic Cluster Resizing. [Citation Graph (0, 0)][DBLP ] Conf ] Petros Drineas , Yiorgos Makris Independent Test Sequence Compaction through Integer Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Seiji Kajihara , Yasumi Doi , Lei Li , Krishnendu Chakrabarty On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Static Test Compaction for Multiple Full-Scan Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinobu Higami , Shin-ya Kobayashi , Yuzo Takamatsu , Seiji Kajihara , Irith Pomeranz A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] C. Ross Ogilvie , Richard Ray , Robert Devins , Mark Kautzman , Michael Hale , Reinaldo A. Bergamaschi , Bob Lynch , Santosh Gaur Simplifying SoC design with the Customizable Control Processor Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Behrooz Zahiri Structured ASICs: Opportunities and Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Sinan Kaptanoglu System LSI Implementation Fabrics for the Future (special panel discussion). [Citation Graph (0, 0)][DBLP ] Conf ] Dongku Kang , Mark C. Johnson , Kaushik Roy Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Su Kwon , Bong-Il Park , Chong-Min Kyung SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushal R. Gandhi , Nihar R. Mahapatra A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units. [Citation Graph (0, 0)][DBLP ] Conf ] Chandramouli Gopalakrishnan , Srinivas Katkoori KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Madhubanti Mukherjee , Ranga Vemuri A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Saraju P. Mohanty , N. Ranganathan , Sunil K. Chappidi Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Farhad Ghasemi-Tari , Peng Rong , Massoud Pedram An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks. [Citation Graph (0, 0)][DBLP ] Conf ] M.-J. Edward Lee , William J. Dally , Ramin Farjad-Rad , Hiok-Tiaq Ng , Ramesh Senthinathan , John H. Edmondson , John Poulton CMOS High-Speed I/Os - Present and Future. [Citation Graph (0, 0)][DBLP ] Conf ] K. Kiziloglu , S. Seetharaman , K. W. Glass , C. Bil , H. V. Duong , G. Asmanis Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Mike P. Li , Jan B. Wilstrup Paradigm Shift For Jitter and Noise In Design and Test > GB/s Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chanik Park , Jaeyu Seo , Dongyoung Seo , Shinhan Kim , Bumsoo Kim Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Premkishore Shivakumar , Stephen W. Keckler , Charles R. Moore , Doug Burger Exploiting Microarchitectural Redundancy For Defect Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Zhijian Lu , John Lach , Mircea R. Stan , Kevin Skadron Reducing Multimedia Decode Power using Feedback Control. [Citation Graph (0, 0)][DBLP ] Conf ] Guoqiang Wang , Andreas Kuehlmann , Alberto L. Sangiovanni-Vincentelli Structural Detection of Symmetries in Boolean Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Elena Dubrova , Maxim Teslenko , Johan Karlsson Boolean Decomposition Based on Cyclic Chains. [Citation Graph (0, 0)][DBLP ] Conf ] Samir Sapra , Michael Theobald , Edmund M. Clarke SAT-Based Algorithms for Logic Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Selvarathinam , Euncheol Kim , Gwan Choi Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels. [Citation Graph (0, 0)][DBLP ] Conf ] Sudeep Pasricha , Alexander V. Veidenbaum Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches. [Citation Graph (0, 0)][DBLP ] Conf ] Santithorn Bunchua , D. Scott Wills , Linda M. Wills Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files. [Citation Graph (0, 0)][DBLP ] Conf ] Matteo Dall'Osso , Gianluca Biccari , Luca Giovannini , Davide Bertozzi , Luca Benini xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Ozgur Sinanoglu , Alex Orailoglu Aggressive Test Power Reduction Through Test Stimuli Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrdad Nourani , James Chin Power-Time Tradeoff in Test Scheduling for SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad H. Tehranipour , Nisar Ahmed , Mehrdad Nourani Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity. [Citation Graph (0, 0)][DBLP ] Conf ] 