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International Conference on Computer Design (ICCD) (iccd)
2003 (conf/iccd/2003)

  1. Mark Horowitz
    High-Speed Link Design, Then and Now. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:- [Conf]
  2. William R. Pulleyblank
    Terascale Computing and BlueGene. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:- [Conf]
  3. Ted Vucurevich
    Advanced EDA Tools for High-Performance Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:- [Conf]
  4. Aneesh Aggarwal, Manoj Franklin
    Energy Efficient Asymmetrically Ported Register Files. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:2-7 [Conf]
  5. Jaume Abella, Antonio González
    Power Efficient Data Cache Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:8-13 [Conf]
  6. Jaume Abella, Antonio González
    On Reducing Register Pressure and Energy in Multiple-Banked Register Files. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:14-20 [Conf]
  7. Masayuki Ito, David G. Chinnery, Kurt Keutzer
    Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:21-0 [Conf]
  8. Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
    Verification of Timed Circuits with Failure Directed Abstractions. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:28-35 [Conf]
  9. Gang Chen, Sudhakar M. Reddy, Irith Pomeranz
    Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:36-41 [Conf]
  10. Marong Phadoongsidhi, Kewal K. Saluja
    Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:42-47 [Conf]
  11. Edmund M. Clarke, Daniel Kroening, Karen Yorav
    Specifying and Verifying Systems with Multiple Clocks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:48-0 [Conf]
  12. Wenjian Yu, Zeyi Wang, Xianlong Hong
    Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:58-63 [Conf]
  13. Chih-Liang Huang, Aurobindo Dasgupta
    An Improved method for Fast Noise Estimation based on Net Segmentation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:64-79 [Conf]
  14. Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein
    Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:70-75 [Conf]
  15. Venkatesan Rajappan, Sachin S. Sapatnekar
    An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:76-0 [Conf]
  16. Payman Zarkesh-Ha, Ken Doniger, William Loh, Dechang Sun, Rick Stephani, Gordon Priebe
    A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:84-89 [Conf]
  17. Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh
    Precomputation-based Guarding for Dynamic and Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:90-97 [Conf]
  18. Saravanan Rajapandian, Zheng Xu, Kenneth L. Shepard
    Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:98-102 [Conf]
  19. Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy
    Low Power Adder with Adaptive Supply Voltage. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:103-106 [Conf]
  20. Nestoras Tzartzanis, William W. Walker
    A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:107-0 [Conf]
  21. Rastislav Levicky
    Detection of Biological Molecules: From Self-Assembled Films to Self-Integrated Devices. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:112-0 [Conf]
  22. Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
    Design Flow Enhancements for DNA Arrays. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:116-0 [Conf]
  23. Nattawut Thepayasuwan, Vaishali Damle, Alex Doboli
    Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:126-133 [Conf]
  24. Vikas Chandra, Gary D. Carpenter, Jeff Burns
    Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:134-139 [Conf]
  25. Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau
    Interface Synthesis using Memory Mapping for an FPGA Platform. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:140-145 [Conf]
  26. Alessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli
    Efficient Synthesis of Networks On Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:146-150 [Conf]
  27. Mehrdad Reshadi, Nikil D. Dutt
    Reducing Compilation Time Overhead in Compiled Simulators. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:151-0 [Conf]
  28. Branden J. Moore, Thomas Slabach, Lambert Schaelicke
    Profiling Interrupt Handler Performance through Kernel Instrumentation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:156-163 [Conf]
  29. Krishna Kant, Ravishankar K. Iyer
    Design and Performance of Compressed Interconnects for High Performance Servers. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:164-169 [Conf]
  30. Karthikeyan Sankaralingam, Vincent Ajay Singh, Stephen W. Keckler, Doug Burger
    Routed Inter-ALU Networks for ILP Scalability and Performance. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:170-0 [Conf]
  31. Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard Davies
    Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:180-186 [Conf]
  32. Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
    Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:187-193 [Conf]
  33. Sobeeh Almukhaizim, Thomas Verdel, Yiorgos Makris
    Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:194-197 [Conf]
  34. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Multiple Fault Diagnosis Using n-Detection Tests. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:198-0 [Conf]
  35. Noriyuki Ito, Hiroaki Komatsu, Yoshiyasu Tanamura, Ryoichi Yamashita, Hiroyuki Sugiyama, Yaroku Sugiyama, Hirofumi Hamamura
    A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:204-210 [Conf]
  36. Yangdong Deng, Wojciech Maly
    Physical Design of the "2.5D" Stacked System. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:211-217 [Conf]
  37. Bo-Kyung Choi, Huaiyu Xu, Maogang Wang, Majid Sarrafzadeh
    Flow-Based Cell Moving Algorithm for Desired Cell Distribution. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:218-0 [Conf]
  38. Byeong Kil Lee, Lizy Kurian John
    NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:226-233 [Conf]
  39. Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan
    Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:234-239 [Conf]
  40. Guy Even, Peter-Michael Seidel
    Pipelined Multiplicative Division with IEEE Rounding. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:240-0 [Conf]
  41. Steven C. Chan, Kenneth L. Shepard, Phillip Restle
    Design of Resonant Global Clock Distributions. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:248-253 [Conf]
  42. Ganesh Balamurugan, Naresh R. Shanbhag
    Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:254-260 [Conf]
  43. Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors
    A Mixed-Mode Delay-Locked-Loop Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:261-263 [Conf]
  44. Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester
    Optimal Inductance for On-chip RLC Interconnections. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:264-0 [Conf]
  45. Nataraj Akkiraju, Mosur Mohan
    Spec Based Flip-Flop And Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:270-275 [Conf]
  46. N. Ranganathan, Ashok K. Murugavel
    A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:276-281 [Conf]
  47. Rishi Chaturvedi, Jiang Hu
    A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:282-0 [Conf]
  48. Shih-Chang Lai, Shih-Lien Lu
    Hardware-based Pointer Data Prefetcher. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:290-298 [Conf]
  49. Sriram Nadathur, Akhilesh Tyagi
    A Dependence Driven Efficient Dispatch Scheme. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:299-306 [Conf]
  50. Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen
    An Efficient VLIW DSP Architecture for Baseband Processing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:307-312 [Conf]
  51. Mohamed M. Zahran, Manoj Franklin
    Dynamic Thread Resizing for Speculative Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:313-0 [Conf]
  52. Bernd Könemann
    Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:320-0 [Conf]
  53. Subhasish Mitra, Kee Sup Kim
    XMAX: X-Tolerant Architecture for MAXimal Test Compression. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:326-330 [Conf]
  54. Janusz Rajski, Jerzy Tyszer
    Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:331-0 [Conf]
  55. Aiqun Cao, Cheng-Kok Koh
    Non-Crossing OBDDs for Mapping to Regular Circuit Structures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:338-343 [Conf]
  56. PariVallal Kannan, Dinesh Bhatia
    Interconnect Estimation for FPGAs under Timing Driven Domains. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:344-349 [Conf]
  57. Hasan Arslan, Shantanu Dutt
    ROAD : An Order-Impervious Optimal Detailed Router for FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:350-0 [Conf]
  58. Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan
    Reducing dTLB Energy Through Dynamic Resizing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:358-363 [Conf]
  59. Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
    Distributed Reorder Buffer Schemes for Low Power. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:364-370 [Conf]
  60. Peter Petrov, Alex Orailoglu
    Virtual Page Tag Reduction for Low-power TLBs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:371-374 [Conf]
  61. José González, Antonio González
    Dynamic Cluster Resizing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:375-0 [Conf]
  62. Petros Drineas, Yiorgos Makris
    Independent Test Sequence Compaction through Integer Programming. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:380-386 [Conf]
  63. Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Chakrabarty
    On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:387-396 [Conf]
  64. Irith Pomeranz, Sudhakar M. Reddy
    Static Test Compaction for Multiple Full-Scan Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:393-396 [Conf]
  65. Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz
    A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:397-0 [Conf]
  66. C. Ross Ogilvie, Richard Ray, Robert Devins, Mark Kautzman, Michael Hale, Reinaldo A. Bergamaschi, Bob Lynch, Santosh Gaur
    Simplifying SoC design with the Customizable Control Processor Platform. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:402-403 [Conf]
  67. Behrooz Zahiri
    Structured ASICs: Opportunities and Challenges. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:404-409 [Conf]
  68. Sinan Kaptanoglu
    System LSI Implementation Fabrics for the Future (special panel discussion). [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:410-0 [Conf]
  69. Dongku Kang, Mark C. Johnson, Kaushik Roy
    Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:412-418 [Conf]
  70. Young-Su Kwon, Bong-Il Park, Chong-Min Kyung
    SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:419-425 [Conf]
  71. Kaushal R. Gandhi, Nihar R. Mahapatra
    A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:426-0 [Conf]
  72. Chandramouli Gopalakrishnan, Srinivas Katkoori
    KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:430-435 [Conf]
  73. Madhubanti Mukherjee, Ranga Vemuri
    A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:436-440 [Conf]
  74. Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi
    Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:441-443 [Conf]
  75. Farhad Ghasemi-Tari, Peng Rong, Massoud Pedram
    An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:444-0 [Conf]
  76. M.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John Poulton
    CMOS High-Speed I/Os - Present and Future. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:454-461 [Conf]
  77. K. Kiziloglu, S. Seetharaman, K. W. Glass, C. Bil, H. V. Duong, G. Asmanis
    Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:462-466 [Conf]
  78. Mike P. Li, Jan B. Wilstrup
    Paradigm Shift For Jitter and Noise In Design and Test > GB/s Communication Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:467-0 [Conf]
  79. Chanik Park, Jaeyu Seo, Dongyoung Seo, Shinhan Kim, Bumsoo Kim
    Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:474-480 [Conf]
  80. Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger
    Exploiting Microarchitectural Redundancy For Defect Tolerance. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:481-488 [Conf]
  81. Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron
    Reducing Multimedia Decode Power using Feedback Control. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:489-0 [Conf]
  82. Guoqiang Wang, Andreas Kuehlmann, Alberto L. Sangiovanni-Vincentelli
    Structural Detection of Symmetries in Boolean Functions. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:498-503 [Conf]
  83. Elena Dubrova, Maxim Teslenko, Johan Karlsson
    Boolean Decomposition Based on Cyclic Chains. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:504-509 [Conf]
  84. Samir Sapra, Michael Theobald, Edmund M. Clarke
    SAT-Based Algorithms for Logic Minimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:510-0 [Conf]
  85. Anand Selvarathinam, Euncheol Kim, Gwan Choi
    Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:520-525 [Conf]
  86. Sudeep Pasricha, Alexander V. Veidenbaum
    Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:526-531 [Conf]
  87. Santithorn Bunchua, D. Scott Wills, Linda M. Wills
    Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:532-535 [Conf]
  88. Matteo Dall'Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini
    xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:536-0 [Conf]
  89. Ozgur Sinanoglu, Alex Orailoglu
    Aggressive Test Power Reduction Through Test Stimuli Transformation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:542-547 [Conf]
  90. Mehrdad Nourani, James Chin
    Power-Time Tradeoff in Test Scheduling for SoCs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:548-553 [Conf]
  91. Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani
    Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:554-0 [Conf]
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NOTICE2
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