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International Conference on Computer Design (ICCD) (iccd)
2004 (conf/iccd/2004)

  1. Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara
    PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:6-11 [Conf]
  2. Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag
    Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:12-17 [Conf]
  3. Justin Hensley, Anselmo Lastra, Montek Singh
    An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:18-25 [Conf]
  4. Robert D. Kenney, Michael J. Schulte, Mark A. Erle
    A High-Frequency Decimal Multiplier. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:26-29 [Conf]
  5. Magnus Själander, Henrik Eriksson, Per Larsson-Edefors
    An Efficient Twin-Precision Multiplier. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:30-33 [Conf]
  6. Aneesh Aggarwal, Manoj Franklin, Oguz Ergin
    Defining Wakeup Width for Efficient Dynamic Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:36-41 [Conf]
  7. Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim
    Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:42-47 [Conf]
  8. Pedro Chaparro, José González, Antonio González
    Thermal-Aware Clustered Microarchitectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:48-53 [Conf]
  9. Yu Bai, R. Iris Bahar
    Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:54-57 [Conf]
  10. Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy
    A Novel Low-Power Scan Design Technique Using Supply Gating. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:60-65 [Conf]
  11. Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
    Asynchronous Scan-Latch controller for Low Area Overhead DFT. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:66-71 [Conf]
  12. Sule Ozev, Alex Orailoglu
    End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:72-77 [Conf]
  13. Ho Fai Ko, Nicola Nicolici
    Functional Illinois Scan Design at RTL. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:78-81 [Conf]
  14. Irith Pomeranz, Sudhakar M. Reddy
    On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:82-84 [Conf]
  15. Hasan Arslan, Shantanu Dutt
    A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:86-92 [Conf]
  16. Tianpei Zhang, Sachin S. Sapatnekar
    Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:93-98 [Conf]
  17. Muhammet Mustafa Ozdal, Martin D. F. Wong
    A Two-Layer Bus Routing Algorithm for High-Speed Boards. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:99-105 [Conf]
  18. Martin D. F. Wong
    Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:106-110 [Conf]
  19. Chao Wang, Gary D. Hachtel, Fabio Somenzi
    Fine-Grain Abstraction and Sequential Don't Cares for Large Scale Model Checking. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:112-118 [Conf]
  20. Miroslav N. Velev
    Comparative Study of Strategies for Formal Verification of High-Level Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:119-124 [Conf]
  21. Srivathsan Krishnamohan, Nihar R. Mahapatra
    A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:126-131 [Conf]
  22. Jihong Ren, Mark R. Greenstreet
    A Signal Integrity Test Bed for PCB Buses. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:132-137 [Conf]
  23. Saumil Shah, Kanak Agarwal, Dennis Sylvester
    A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:138-143 [Conf]
  24. John Lach, Jason Brandon, Kevin Skadron
    A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:144-150 [Conf]
  25. Davide Pandini, Cristiano Forzan, Livio Baldi
    Design Methodologies and Architecture Solutions for High-Performance Interconnects. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:152-159 [Conf]
  26. Mario R. Casu, Luca Macchiarulo
    On-Chip Transparent Wire Pipelining. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:160-167 [Conf]
  27. Radu Marculescu, Diana Marculescu, Larry T. Pileggi
    Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:168-173 [Conf]
  28. Gérard Mas, Philippe Martin
    Network-on-Chip: The Intelligence is in The Wire. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:174-177 [Conf]
  29. Jinkyu Lee, Nur A. Touba
    Low Power Test Data Compression Based on LFSR Reseeding. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:180-185 [Conf]
  30. Jui-Jer Huang, Jiun-Lang Huang
    An Infrastructure IP for On-Chip Clock Jitter Measurement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:186-191 [Conf]
  31. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Diagnosis of Hold Time Defects. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:192-199 [Conf]
  32. Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu
    Extending the Applicability of Parallel-Serial Scan Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:200-203 [Conf]
  33. Roy Emek, Itai Jaeger, Yoav Katz, Yehuda Naveh
    Quality Improvement Methods for System-Level Stimuli Generation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:204-206 [Conf]
  34. Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma
    XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:208-215 [Conf]
  35. Ruiming Chen, Hai Zhou
    A Flexible Data Structure for Efficient Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:216-221 [Conf]
  36. Madhubanti Mukherjee, Ranga Vemuri
    Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:222-227 [Conf]
  37. Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
    Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:228-233 [Conf]
  38. Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang
    Best of Both Latency and Throughput. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:236-243 [Conf]
  39. Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss
    Fetch Halting on Critical Load Misses. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:244-249 [Conf]
  40. Grigorios Magklis, José González, Antonio González
    Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:250-255 [Conf]
  41. Feng Gao, John P. Hayes
    Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:258-264 [Conf]
  42. Kai Wang, Malgorzata Marek-Sadowska
    Potential Slack Budgeting with Clock Skew Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:265-271 [Conf]
  43. Murari Mani, Michael Orshansky
    A New Statistical Optimization Algorithm for Gate Sizing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:272-277 [Conf]
  44. Mark A. Franklin, Roger D. Chamberlain, Michael Henrichs, Berkley Shands, Jason White
    An Architecture for Fast Processing of Large Unstructured Data Sets. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:280-287 [Conf]
  45. Roland E. Wunderlich, James C. Hoe
    In-System FPGA Prototyping of an Itanium Microarchitecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:288-294 [Conf]
  46. Chun-Ho Kim, Lee-Sup Kim
    Adaptive Selection of an Index in a Texture Cache. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:295-300 [Conf]
  47. Michael T. Niemier, Ramprasad Ravichandran, Peter M. Kogge
    Using Circuits and Systems-Level Research to Drive Nanotechnology. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:302-309 [Conf]
  48. Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka
    FPGA Emulation of Quantum Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:310-315 [Conf]
  49. Bryan Black, Donald Nelson, Clair Webb, Nick Samra
    3D Processing Technology and Its Impact on iA32 Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:316-318 [Conf]
  50. Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutmann
    Cache Array Architecture Optimization at Deep Submicron Technologies. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:320-325 [Conf]
  51. Joshua L. Kihm, Daniel A. Connors
    Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:326-331 [Conf]
  52. Alexander V. Veidenbaum, Dan Nicolaescu
    Low Energy, Highly-Associative Cache Design for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:332-335 [Conf]
  53. Yajun Ran, Malgorzata Marek-Sadowska
    The Magic of a Via-Configurable Regular Fabric. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:338-343 [Conf]
  54. Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan
    A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:344-349 [Conf]
  55. Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz
    Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:350-353 [Conf]
  56. Dongku Kang, Hunsoo Choo, Kaushik Roy
    Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:354-357 [Conf]
  57. Srikanth T. Srinivasan, Haitham Akkary, Tom Holman, Konrad Lai
    A Minimal Dual-Core Speculative Multi-Threading Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:360-367 [Conf]
  58. Rama Sangireddy, Arun K. Somani
    Exploiting Quiescent States in Register Lifetime. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:368-374 [Conf]
  59. Yau Chin, John Sheu, David Brooks
    Evaluating Techniques for Exploiting Instruction Slack. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:375-378 [Conf]
  60. Siddharth Garg, Siddharth Tata, Ravishankar Arunachalam
    Static Transition Probability Analysis Under Uncertainty. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:380-386 [Conf]
  61. Donald Chai, Andreas Kuehlmann
    Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:387-392 [Conf]
  62. Mirko Loghi, Luca Benini, Massimo Poncino
    Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:393-396 [Conf]
  63. Zhaohui Huang, Peixin Zhong
    An Architectural Power Estimator for Analog-to-Digital Converters. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:397-400 [Conf]
  64. Nikhil Kikkeri, Peter-Michael Seidel
    Formal Hardware Verification based on Signal Correlation Properties. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:402-408 [Conf]
  65. Kelvin Ng, Alan J. Hu, Jin Yang
    Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:409-416 [Conf]
  66. Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou
    Graph Automorphism-Based Algorithm for Determining Symmetric Inputs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:417-419 [Conf]
  67. Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod
    Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:422-429 [Conf]
  68. Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin
    Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:430-437 [Conf]
  69. Chan-Eun Rhee, Han-You Jeong, Soonhoi Ha
    Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:438-443 [Conf]
  70. Liang Han, Jie Chen, Chaoxian Zhou, Ying Li, Xin Zhang, Zhibi Liu, Xiaoyun Wei, Baofeng Li
    An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:446-451 [Conf]
  71. A. Murat Fiskiran, Ruby B. Lee
    Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:452-457 [Conf]
  72. Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra
    Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:458-463 [Conf]
  73. Feng Shi, Sobeeh Almukhaizim, Pey-Chang Lin, Yiorgos Makris
    Compiler-Based Frame Formation for Static Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:466-471 [Conf]
  74. Sriram Nadathur, Akhilesh Tyagi
    IPC Driven Dynamic Associative Cache Architecture for Low Energy. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:472-479 [Conf]
  75. Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kanad Ghose
    Increasing Processor Performance Through Early Register Release. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:480-487 [Conf]
  76. Hu Huang, Joseph B. Bernstein, Martin Peckerar, Ji Luo
    Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of Field. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:490-495 [Conf]
  77. Franco Fummi, Stefano Martini, Marco Monguzzi, Giovanni Perbellini, Massimo Poncino
    Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:496-501 [Conf]
  78. Jinwen Xi, Peixin Zhong
    Hardware/Software Co-Modeling of SAT Solver Based on Distributed Computing Elements using SystemC. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:502-504 [Conf]
  79. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou
    Coping with The Variability of Combinational Logic Delays. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:505-508 [Conf]
  80. Vassos Soteriou, Li-Shiuan Peh
    Design-Space Exploration of Power-Aware On/Off Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:510-517 [Conf]
  81. Yao Guo, Saurabh Chheda, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
    Energy Characterization of Hardware-Based Data Prefetching. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:518-523 [Conf]
  82. Hee-Kwan Son, Sang-Geun Oh
    Design and Implementation of Scalable Low-Power Montgomery Multiplier. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:524-531 [Conf]
  83. Scott Ollivierre, Adam B. Kinsman, Nicola Nicolici
    Compressed Embedded Diagnosis of Logic Cores. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:534-539 [Conf]
  84. Pallav Gupta, Rui Zhang, Niraj K. Jha
    An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:540-543 [Conf]
  85. Hung-Yau Lin, Hong-Zu Chou, Fu-Min Yeh, Ing-Yi Chen, Sy-Yen Kuo
    An Efficient Algorithm for Reconfiguring Shared Spare RRAM. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:544-546 [Conf]
  86. Hashem Hashemi Najaf-abadi, Hamid Sarbazi-Azad
    An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:548-553 [Conf]
  87. Raymond W. Baldwin, Enrico Ng
    Technique to Eliminate Sorting in IP Packet Forwarding Devices. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:554-559 [Conf]
  88. Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang
    I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:562-567 [Conf]
  89. Meng-Chen Wu, Yao-Wen Chang
    Placement with Alignment and Performance Constraints Using the B*-Tree Representation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:568-571 [Conf]
  90. Hai Zhou, Jia Wang
    ACG-Adjacent Constraint Graph for General Floorplans. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:572-575 [Conf]
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