Conferences in DBLP
Alberto Ferrari , Alberto L. Sangiovanni-Vincentelli System Design: Traditional Concepts and New Paradigms. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt Keutzer , A. Richard Newton The MARCO/DARPA Gigascale Silicon Research Center. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Wolf CAD Techniques for Embedded Systems-on-Silicon. [Citation Graph (0, 0)][DBLP ] Conf ] Eduard Cerny , Fen Jin Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Ghosh , Ranga Vemuri Formal Verification of Synthesized Analog Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Ted Stanion Implicit Verification of Structurally Dissimilar Arithmetic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk W. Hoffmann , Thomas Kropf Automatic Error Correction of Tri-State Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Sumio Morioka , Yasunao Katayama Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Jae Hun Choi , Jae-Hyuck Kwak , Earl E. Swartzlander Jr. High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection. [Citation Graph (0, 0)][DBLP ] Conf ] Tomás Lang , Javier D. Bruguera Multilevel Reverse-Carry Computation for Comparison and for Sign and Overflow Detection in Addition. [Citation Graph (0, 0)][DBLP ] Conf ] William L. Freking , Keshab K. Parhi A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Scott , Lea Hwang Lee , Ann Chin , John Arends , Bill Moyer Designing the M·CORETM M3 CPU Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Clark , Lizy Kurian John Performance Evaluation of Configurable Hardware Features on the AMD-K5. [Citation Graph (0, 0)][DBLP ] Conf ] Qiang Cao , Josep Torrellas , Pedro Trancoso , Josep-Lluis Larriba-Pey , Bob Knighten , Youjip Won Detailed Characterization of a Quad Pentium Pro Server Running TPC-D. [Citation Graph (0, 0)][DBLP ] Conf ] Nathan Kalyanasundharam , Nital Patwa Simultaneous Switching Noise Considerations in the Design of a High Speed, Multiported TLB of a Server-Class Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Srivatsan Srinivasan , Lizy Kurian John On the Use of Pseudorandom Sequences for High Speed Resource Allocators in Superscalar Processors. [Citation Graph (0, 0)][DBLP ] Conf ] William Fornaciari , Donatella Sciuto , Cristina Silvano Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Tor E. Jeremiassen A DSP with Caches-A Study of the GSM-EFR Codec on the TI C6211. [Citation Graph (0, 0)][DBLP ] Conf ] David L. Landis , Paul T. Hulina , Scott Deno , Luke Roth , Lee D. Coraor Evaluation of Computing in Memory Architectures for Digital Image Processing Applications. [Citation Graph (0, 0)][DBLP ] Conf ] You-Sung Chang , Bong-Il Park , In-Cheol Park , Chong-Min Kyung Customization of a CISC Processor Core for Low-Power Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Hangkyu Lee , Sungho Kang A New Weight Set Generation Algorithm for Weighted Random Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Dufaza Multiple Paths Sensitization of Digital Oscillation Built-In Self Test. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Chang , Brion L. Keller , Sarala Paliwal Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Jang-Soo Lee , Won-Kee Hong , Shin-Dug Kim Design and Evaluation of a Selective Compressed Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] Yi Kang , Wei Huang , Seung-Moon Yoo , Diana Keen , Zhenzhou Ge , Vinh Vi Lam , Josep Torrellas , Pratap Pattnaik FlexRAM: Toward an Advanced Intelligent Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Oskin , Frederic T. Chong , Timothy Sherwood ActiveOS: Virtualizing Intelligent Memory. [Citation Graph (0, 0)][DBLP ] Conf ] I-Min Liu , Adnan Aziz , D. F. Wong , Hai Zhou An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] K. K. Lee , D. F. Wong An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Chunhong Chen , Majid Sarrafzadeh An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Khurram Muhammad , Dinesh Somasekhar , Kaushik Roy Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Nannarelli , Tomás Lang Low-Power Radix-4 Combined Division and Square Root. [Citation Graph (0, 0)][DBLP ] Conf ] Bong-Il Park , In-Cheol Park , Chong-Min Kyung A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Narendra V. Shenoy , Mahesh A. Iyer , Robert F. Damiano , Kevin Harer , Hi-Keung Tony Ma , Paul Thilking A Robust Solution to the Timing Convergence Problem in High-Performance Design. [Citation Graph (0, 0)][DBLP ] Conf ] Wilm E. Donath , Prabhakar Kudva , Lakshmi N. Reddy Performance Driven Optimization of Network Length in Physical Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Kuhlmann , Sachin S. Sapatnekar , Keshab K. Parhi Efficient Crosstalk Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Hasan Cam , Mostafa H. Abd-El-Barr , Sadiq M. Sait A High-Performance Hardware-Efficient Memory Allocation Technique and Design. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Hakenes , Yiannos Manoli Improving Microcontroller Power Consumption through a Segmented Gray Code Program Counter. [Citation Graph (0, 0)][DBLP ] Conf ] Kentaro Shimada , Tatsuya Kawashimo , Makoto Hanawa , Ryo Yamagata , Eiki Kamada A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh Radhakrishnan , Juan Rubio , Lizy Kurian John Characterization of Java Applications at Bytecode and Ultra-SPARC Machine Code Levels. [Citation Graph (0, 0)][DBLP ] Conf ] Avinash K. Gautam , V. Visvanathan , S. K. Nandy Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. [Citation Graph (0, 0)][DBLP ] Conf ] G. S. Samudra , H. M. Chen , D. S. H. Chan , Yaacob Ibrahim Yield Optimization by Design Centering and Worst-Case Distance Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Thomas , Brian Anthony Area, Performance, and Yield Implications of Redundancy in On-Chip Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Walling R. Cyre Conceptual Modeling and Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Peter James Aldworth System-on-a-Chip Bus Architecture for Embedded Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Kyoung-Mook Lim , Seh-Woong Jeong , Yong-Chun Kim , Seung-Jae Jeong , Hong-Kyu Kim , Yang-Ho Kim , Bong-Young Chung , Hyung-Lae Roh , H. S. Yang CalmRISCTM : A Low Power Microcontroller with Efficient Coprocessor Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Shuenn-Shi Chen , Jong-Jang Chen , Sao-Jie Chen , Chia-Chun Tsai An Even Wiring Approach to the Ball Grid Array Package Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Per Lindgren , Rolf Drechsler , Bernd Becker Synthesis of Pseudo Kronecker Lattice Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Shyu , Yu-Dong Chang , Guang-Ming Wu , Yao-Wen Chang Generic Universal Switch Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald W. Mehler , M. Ray Mercer Multi-Level Logic Minimization through Fault Dictionary Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Kang Yi , Seong Yong Ohm A Fast and Exact Cell Matching Method for MUX-Based FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Kumar , Magdy A. Bayoumi Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-Nan Jimmy Liu , Jing-Yang Jou An Efficient Functional Coverage Test for HDL Descriptions at RTL. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunjin Kim , Jongchul Shin , Sungho Kang An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment. [Citation Graph (0, 0)][DBLP ] Conf ] J. Velasco-Medina , Iyad Rayane , Michael Nicolaidis On-Line BIST for Testing Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Avinash K. Gautam , Jagdish C. Rao , Karthikeyan Madathil , Vilesh Shah , H. Udayakumar , Amitabh Menon , Subash G. Chandar A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Sari L. Coumeri , Donald E. Thomas An Environment for Exploring Low Power Memory Configurations in System Level Design. [Citation Graph (0, 0)][DBLP ] Conf ] Brandon M. Bachman , Hao Zheng , Chris J. Myers Architectural Synthesis of Timed Asynchronous Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hen-Ming Lin , Jing-Yang Jou Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD. [Citation Graph (0, 0)][DBLP ] Conf ] Steven P. Vanderwiel , David J. Lilja A Compiler-Assisted Data Prefetch Controller. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos Bellas , Ibrahim N. Hajj , Constantine D. Polychronopoulos , George D. Stamoulis Energy and Performance Improvements in Microprocessor Design Using a Loop Cache. [Citation Graph (0, 0)][DBLP ] Conf ] Priyadarshan Kolte , Roger Smith , Su Wen A Fast Median Filter Using AltiVec. [Citation Graph (0, 0)][DBLP ] Conf ] Guo-Hui Lin , Guoliang Xue , Defang Zhou Approximating Hexagonal Steiner Minimal Trees by Fast Optimal Layout of Minimum Spanning Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Sreenivas Mandava , Sreejit Chakravarty , Sandip Kundu On Detecting Bridges Causing Timing Failures. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Savir Design for Testability to Combat Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Jas , Nur A. Touba Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Lucian Codrescu , D. Scott Wills Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Hung Chi , Jun-Li Yuan Load-Balancing Branch Target Cache and Prefetch Buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Akhilesh Tyagi , Hon-Chi Ng , Prasant Mohapatra Dynamic Branch Decoupled Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Robert W. Sumners , Jayanta Bhadra , Jacob A. Abraham Improving Witness Search Using Orders on States. [Citation Graph (0, 0)][DBLP ] Conf ] Pranav Ashar , Anand Raghunathan , Aarti Gupta , Subhrajit Bhattacharya Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Kavita Ravi , Fabio Somenzi Efficient Fixpoint Computation for Invariant Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Mauro Olivieri , Alessandro Trifiletti , Alessandro De Gloria A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sree Ganesan , Ranga Vemuri A Methodology for Rapid Prototyping of Analog Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Becker , Thomas F. Knight Jr. Transmission Line Clock Driver. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Weiss Benchmarking, Selection and Debugging of Microcontrollers. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald Stence A New Development Tool with the IEEE-ISTO. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald Stence 32-Bit Architectures for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Donald Steiss The Specialization of General Purpose Processor Architecture Elements for Programmable Digital Signal Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Uming Ko , Mike McMahan , Edgar Auslander DSP for the Third Generation Wireless Communications. [Citation Graph (0, 0)][DBLP ] Conf ] Nagaraj Ns , Frank Cano , Sudha Thiruvengadam , Deepak Kapoor Performance and Reliability Verification of C6201/C6701 Digital Signal Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Peter van Vleet , Eric J. Anderson , Lindsay Brown , Jean-Loup Baer , Anna R. Karlin Pursuing the Performance Potential of Dynamic Cache Line Sizes. [Citation Graph (0, 0)][DBLP ] Conf ] Brian R. Fisk , R. Iris Bahar The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro Trancoso , Josep Torrellas Cache Optimization for Memory-Resident Decision Support Commercial Workloads. [Citation Graph (0, 0)][DBLP ] Conf ] Qi Wang , Sarma B. K. Vrudhula An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Maitham Shams , Mohamed I. Elmasry Delay Optimization of CMOS Logic Circuits Using Closed-Form Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Tyler Thorp , Gin Yee , Carl Sechen Design and Synthesis of Monotonic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] J. V. Tran , Farnaz Mounes-Toussi , S. N. Storino , D. L. Stasiak SOI Implementation of a 64-Bit Adder. [Citation Graph (0, 0)][DBLP ] Conf ] Harvey G. Cragon Forty Five Years of Computer Architecture-All That's Old is New Again. [Citation Graph (0, 0)][DBLP ] Conf ] A. K. Riemens , Kees A. Vissers , R. J. Schutten , Gerben J. Hekstra , G. D. La Hei , Frans Sijstermans TriMedia CPU64 Application Domain and Benchmark Suite. [Citation Graph (0, 0)][DBLP ] Conf ] Jos T. J. van Eijndhoven , Kees A. Vissers , Evert-Jan D. Pol , P. Struik , R. H. J. Bloks , Pieter van der Wolf , Harald P. E. Vranken , Frans Sijstermans , M. J. A. Tromp , Andy D. Pimentel TriMedia CPU64 Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Evert-Jan D. Pol , Bas Aarts , Jos T. J. van Eijndhoven , P. Struik , Pieter van der Wolf , Frans Sijstermans , M. J. A. Tromp , Jan-Willem van de Waerdt TriMedia CPU64 Application Development Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Gerben J. Hekstra , G. D. La Hei , Peter Bingley , Frans Sijstermans TriMedia CPU64 Design Space Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Imtiaz Ahmad , Raza Ul-Mustafa On State Assignment of Finite State Machines Using Hypercube Embedding Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Pradip K. Jha , Steven Barnfield , John B. Weaver , Rudra Mukherjee , Reinaldo A. Bergamaschi Synthesis of Arrays and Records. [Citation Graph (0, 0)][DBLP ] Conf ] Rupesh S. Shelar , Madhav P. Desai , H. Narayanan Decomposition of Finite State Machines for Area, Delay Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Congguang Yang , Maciej J. Ciesielski , Vigyan Singhal BDD Decomposition for Efficient Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Felice Balarin , Massimiliano Chiodo Software Synthesis for Complex Reactive Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Romain Kamdem , Alain Fonkoua , Andre Zenatti Hardware/Software Partitioning of Multirate System Using Static Scheduling Theory. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaohan Zhu , Bill Lin Compositional Software Synthesis of Communicating Processes. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Quan , Xiaobo Hu , Garrison W. Greenwood Preference-Driven Hierarchical Hardware/Software Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] 