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Conferences in DBLP

International Conference on Computer Design (ICCD) (iccd)
2000 (conf/iccd/2000)

  1. Dirk Friebel
    On the Road to a Mobile Information Society. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:3-0 [Conf]
  2. Krishna Kant, Ravishankar K. Iyer, Prasant Mohapatra
    Architectural Impact of Secure Socket Layer on Internet Servers. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:7-14 [Conf]
  3. Xiao Yang, Ruby B. Lee
    Fast Subword Permutation Instructions Using Omega and Flip Network Stages. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:15-21 [Conf]
  4. Tor E. Jeremiassen
    Sleipnir - An Instruction-Level Simulator Generator. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:23-0 [Conf]
  5. Junwei Hou, Abhijit Chatterjee
    Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:35-41 [Conf]
  6. Dimitrios Kagaris, Spyros Tragoudas
    Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:42-47 [Conf]
  7. Fabrizio Ferrandi, Donatella Sciuto, Alessandro Fin, Franco Fummi
    An Application of Genetic Algorithms and BDDs to Functional Testing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:48-0 [Conf]
  8. Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang
    High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:59-64 [Conf]
  9. Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
    Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:65-72 [Conf]
  10. Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson
    Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:73-0 [Conf]
  11. Martin Burtscher, Benjamin G. Zorn
    Hybridizing and Coalescing Load Value Predictors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:81-92 [Conf]
  12. Yul Chu, Mabo Robert Ito
    A 2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented Languages. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:93-98 [Conf]
  13. J. Morris Chang, Witawas Srisa-an, Chia-Tien Dan Lo
    Architectural Support for Dynamic Memory Management. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:99-104 [Conf]
  14. Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku
    SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:105-0 [Conf]
  15. Tong Xiao, Malgorzata Marek-Sadowska
    Worst Delay Estimation in Crosstalk Aware Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:115-120 [Conf]
  16. Payam Heydari, Massoud Pedram
    Analysis and Optimization of Ground Bounce in Digital CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:121-126 [Conf]
  17. Nasser Masoumi, Safieddin Safavi-Naeini, Mohamed I. Elmasry
    An Efficient and Accurate Model for RF/Microwave Spiral Inductors Using Microstrip Lines Theory. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:127-132 [Conf]
  18. Yanhong Yuan, Prithviraj Banerjee
    Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:133-0 [Conf]
  19. Rolf Hakenes, Yiannos Manoli
    A Novel Low-Power Microprocessor Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:141-146 [Conf]
  20. Rafael A. Moreno, Luis Piñuel, Silvia Del Pino, Francisco Tirado
    A Power Perspective of Value Speculation for Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:147-154 [Conf]
  21. Javier D. Bruguera, Tomás Lang
    Multilevel Reverse-Carry Adder. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:155-162 [Conf]
  22. Deependra Talla, Lizy Kurian John, Viktor S. Lapinskii, Brian L. Evans
    Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:163-0 [Conf]
  23. Qiang Cao, Josep Torrellas, H. V. Jagadish
    Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:175-186 [Conf]
  24. Jeffrey B. Rothman, Alan Jay Smith
    Analysis of Shared Memory Misses and Reference Patterns. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:187-198 [Conf]
  25. John S. Seng, Dean M. Tullsen, George Cai
    Power-Sensitive Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:199-0 [Conf]
  26. I-Min Liu, Adnan Aziz
    Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:209-214 [Conf]
  27. Yi-Kan Cheng, David Bearden, Kanti Suryadevara
    Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPCTM Microprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:215-220 [Conf]
  28. José Luis Neves, Stephen T. Quay
    Buffer Library Selection. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:221-226 [Conf]
  29. Naran Sirisantana, Liqiong Wei, Kaushik Roy
    High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:227-0 [Conf]
  30. Sudhakar Bobba, Ibrahim N. Hajj
    Current-Mode Threshold Logic Gates. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:235-240 [Conf]
  31. Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar
    Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:241-246 [Conf]
  32. Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen
    Output Prediction Logic: A High-Performance CMOS Design Technique. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:247-0 [Conf]
  33. Gregory F. Pfister
    The Future of Populist Parallelism. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:257- [Conf]
  34. Lars Friebe, Yoshikazu Yabe, Masato Motomura
    A Study of Channeled DRAM Memory Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:261-266 [Conf]
  35. Haifeng Yu, Gershon Kedem
    DRAM-Page Based Prediction and Prefetching. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:267-275 [Conf]
  36. Mark Oskin, Diana Keen, Justin Hensley, Lucian Vlad Lita, Frederic T. Chong
    Reducing Cost and Tolerating Defects in Page-based Intelligent Memory. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:276-0 [Conf]
  37. Jung-Hoon Lee, Jang-Soo Lee, Shin-Dug Kim
    A Selective Temporal and Aggressive Spatial Cache System Based on Time Interval. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:287-293 [Conf]
  38. Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung
    Design of Instruction Stream Buffer with Trace Support for X86 Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:294-299 [Conf]
  39. Anshuman S. Nadkarni, Akhilesh Tyagi
    A Trace Based Evaluation of Speculative Branch Decoupling. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:300-0 [Conf]
  40. Hak-soo Yu, Songjun Lee, Jacob A. Abraham
    An Adder Using Charge Sharing and its Application in DRAMs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:311-317 [Conf]
  41. Shyh-Jye Jou, Hui-Hsuan Wang
    Fixed-Width Multiplier for DSP Application. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:318-322 [Conf]
  42. Nikola Nedovic, Vojin G. Oklobdzija
    Dynamic Flip-Flop with Improved Power. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:323-0 [Conf]
  43. Stephen B. Furber, David A. Edwards, Jim D. Garside
    AMULET3: A 100 MIPS Asynchronous Embedded Processor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:329-334 [Conf]
  44. Gülbin Ezer
    Xtensa with User Defined DSP Coprocessor Microarchitectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:335-342 [Conf]
  45. Pavan Kumar, Mani B. Srivastava
    Predictive Strategies for Low-Power RTOS Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:343-0 [Conf]
  46. Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang
    Rectilinear Block Placement Using B*-Trees. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:351-356 [Conf]
  47. Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh
    Fast Hierarchical Floorplanning with Congestion and Timing Control. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:357-362 [Conf]
  48. Elie Yarack, Joan Carletta
    An Evaluation of Move-Based Multi-Way Partitioning Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:363-369 [Conf]
  49. Koji Ohashi, Mineo Kaneko, Satoshi Tayu
    Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:370-0 [Conf]
  50. Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah
    On Solving Stack-Based Incremental Satisfiability Problems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:379-382 [Conf]
  51. Wolfgang Günther, Rolf Drechsler, Stefan Höreth
    Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:383-388 [Conf]
  52. Irith Pomeranz, Sudhakar M. Reddy
    Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:389-394 [Conf]
  53. Irith Pomeranz, Sudhakar M. Reddy
    On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:395-0 [Conf]
  54. Tim Anderson, Sanjive Agarwala
    Effective Hardware-Based Two-Way Loop Cache for High Performance Low Power Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:403-407 [Conf]
  55. Sanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley
    A Multi-Level Memory System Architecture for High-Performance DSP Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:408-413 [Conf]
  56. Dave Comisky, Sanjive Agarwala, Charles Fuoco
    A Scalable High-Performance DMA Architecture for DSP Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:414-0 [Conf]
  57. Srihari Cadambi, Seth Copen Goldstein
    Efficient Place and Route for Pipeline Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:423-429 [Conf]
  58. Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi
    PEAS-III: An ASIP Design Environment. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:430-436 [Conf]
  59. Satish Pillai, Margarida F. Jacome
    Symbolic Binding for Clustered VLIW ASIPs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:437-444 [Conf]
  60. Dinesh Ramanathan, Rajesh K. Gupta, Raymond Roth
    Interfacing Hardware and Software Using C++ Class Libraries. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:445-0 [Conf]
  61. Hoon Choi, Myung-Kyoon Yim, Jae Young Lee, Byeong-Whee Yun, Yun-Tae Lee
    Formal Verification of an Industrial System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:453-458 [Conf]
  62. Viresh Paruthi, Andreas Kuehlmann
    Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:459-464 [Conf]
  63. Dirk W. Hoffmann, Thomas Kropf
    Efficient Design Error Correction of Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:465-472 [Conf]
  64. Michael Cogswell, Don Pearl, James Sage, Alan Troidl
    An Automatic Validation Methodology for Logic BIST in High Performance VLSI Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:473-0 [Conf]
  65. Hilary J. Kahn, R. B. E. Napper
    The Birth of the Baby. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:481-0 [Conf]
  66. Thomas Kutzschebauch
    Efficient Logic Optimization Using Regularity Extraction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:487-493 [Conf]
  67. Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:494-503 [Conf]
  68. Per Lindgren, Rolf Drechsler, Bernd Becker
    Minimization of Ordered Pseudo Kronecker Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:504-0 [Conf]
  69. Wander O. Cesário, Ahmed Amine Jerraya, Zoltan Sugar, Imed Moussa
    Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:513-518 [Conf]
  70. Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min Kyung
    Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:519-524 [Conf]
  71. F. Hessel, P. Coste, Gabriela Nicolescu, P. LeMarrec, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
    Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:525-0 [Conf]
  72. Wael M. Badawy, Magdy A. Bayoumi
    Low Power Video Object Motion-Tracking Architecture for Very Low Bit Rate Online Video Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:533-536 [Conf]
  73. Alfredo Benso, Stefano Martinetto, Paolo Prinetto, Riccardo Mariani
    An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:537-538 [Conf]
  74. Alfredo Benso, Stefano Di Carlo, Silvia Chiusano, Paolo Prinetto, Fabio Ricciato, Monica Lobetti Bodoni, Maurizio Spadari
    On Integrating a Proprietary and a Commercial Architecture for Optimal BIST Performances in SoCs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:539-540 [Conf]
  75. Haizhou Chen, Bing Lu, Ding-Zhu Du
    Static Timing Analysis with False Paths. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:541-544 [Conf]
  76. Joachim Gerlach, Wolfgang Rosenstiel
    A Methodology and Tool for Automated Transformational High-Level Design Space Exploration. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:545-548 [Conf]
  77. J. P. Grossman
    Cheap Out-of-Order Execution Using Delayed Issue. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:549-551 [Conf]
  78. Steve Haynal, Forrest Brewer
    Representing and Scheduling Looping Behavior Symbolically. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:552-555 [Conf]
  79. Toru Hiyama, Yuko Ito, Satoru Isomura, Kazunobu Nojiri, Eijiro Maeda
    Advanced Wiring RC Timing Design Techniques for Logic LSIs in Gigahertz Era and Beyond. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:556-558 [Conf]
  80. Yoochang Jung, Stefan G. Berg, Donglok Kim, Yongmin Kim
    A Register File with Transposed Access Mode. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:559-560 [Conf]
  81. Kamal S. Khouri, Niraj K. Jha
    Leakage Power Analysis and Reduction during Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:561-564 [Conf]
  82. Austin Kim, J. Morris Chang
    An Advanced Instruction Folding Mechanism for a Stackless Java Processor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:565-566 [Conf]
  83. Hemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha Chandrakasan
    OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:567-570 [Conf]
  84. Haris Lekatsas, Jörg Henkel, Wayne Wolf
    A Decompression Architecture for Low Power Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:571-574 [Conf]
  85. Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh
    Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:575-576 [Conf]
  86. Afzal Malik, Bill Moyer, Dan Cermak
    The M·CORETM M340 Unified Cache Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:577-580 [Conf]
  87. Song-Ra Pan, Yao-Wen Chang
    Crosstalk-Constrained Performance Optimization by Using Wire Sizing and Perturbation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:581-584 [Conf]
  88. Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra
    Hierarchical Simulation of a Multiprocessor Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:585-588 [Conf]
  89. Hagen Ploog, Dirk Timmermann
    On Multiple Precision Based Montgomery Multiplication without Precomputation of N0´ = -N0-1 mod W. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:589-590 [Conf]
  90. Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana
    A Technique for Identifying RTL and Gate-Level Correspondences. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:591-0 [Conf]
  91. John T. Welch, Joan Carletta
    A Direct Mapping FPGA Architecture for Industrial Process Control Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:595-598 [Conf]
  92. Brian D. Winters, Alan J. Hu
    Source-Level Transformations for Improved Formal Verification. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:599-0 [Conf]
  93. Farinaz Koushanfar, Miodrag Potkonjak, Vandana Prabhu, Jan M. Rabaey
    Processors for Mobile Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:603-608 [Conf]
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