The SCEAS System
Navigation Menu

Conferences in DBLP

International Conference on Evolvable Systems (ICES) (ices)
1996 (conf/ices/1996)

  1. Igor Aleksander
    Iconic Learning in Networks of Logical Neurons. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:3-16 [Conf]
  2. William Ward Armstrong
    Hardware Requirements for Fast Evaluation of Functions Learned by Adaptive Logic Networks. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:17-22 [Conf]
  3. Shinichi Shiratsuchi
    FPGA as a Key Component for Reconfigurable System. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:23-32 [Conf]
  4. Eduardo Sanchez, Daniel Mange, Moshe Sipper, Marco Tomassini, Andrés Pérez-Uribe, André Stauffer
    Phylogeny, Ontogeny, and Epigenesis: Three Sources of Biological Inspiration for Softening Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:35-54 [Conf]
  5. Xin Yao, Tetsuya Higuchi
    Promises and Challenges of Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:55-78 [Conf]
  6. Moshe Sipper
    Designing Evolware by Cellular Programming. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:81-95 [Conf]
  7. Maxime Goeke, Moshe Sipper, Daniel Mange, André Stauffer, Eduardo Sanchez, Marco Tomassini
    Online Autonomous Evolware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:96-106 [Conf]
  8. Pierre Marchal, Pascal Nussbaum, Christian Piguet, Moshe Sipper
    Speeding-up Digital Ecologies Evolution Using a Hardware Emulator: Preliminary Results. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:107-124 [Conf]
  9. Hiroaki Kitano
    Challenges of Evolvable Systems: Analysis and Future Directions. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:125-135 [Conf]
  10. Pascal Nussbaum, Pierre Marchal, Christian Piguet
    Functional Organisms Growing on Silicon. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:139-151 [Conf]
  11. Kenichi Morita, Katsunobu Imai
    Logical Universality and Self-Reproduction in Reversible Cellular Automata. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:152-166 [Conf]
  12. Mehrdad Salami, Masahiro Murakawa, Tetsuya Higuchi
    Data Compression Based on Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:169-179 [Conf]
  13. Weixin Liu, Masahiro Murakawa, Tetsuya Higuchi
    ATM Cell Scheduling by Function Level Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:180-192 [Conf]
  14. Didier Keymeulen, Marc Durantez, Kenji Konaka, Yasuo Kuniyoshi, Tetsuya Higuchi
    An Evolutionary Robot Navigation System Using a Gate-Level Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:195-209 [Conf]
  15. Taku Naito, Ryoichi Odagiri, Yutaka Matsunaga, Manabu Tanifuji, Kazuyuki Murase
    Genetic Evolution of a Logic Circuit which Controls an Autonomous Mobile Robot. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:210-219 [Conf]
  16. Jun Yamamoto, Yuichiro Anzai
    Autonomous Robot with Evolving Algorithm Based on Biological Systems. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:220-233 [Conf]
  17. Hidetaka Ito, Tatsumi Furuya
    Memory-Based Neural Network and Its Application to a Mobile Robot with Evolutionary and Experience Learning. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:234-246 [Conf]
  18. Mehrdad Salami
    Multiple Genetic Algorithm Processor for Hardware Optimization. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:249-259 [Conf]
  19. John S. McCaskill, Thomas Maeke, Udo Gemm, Ludger Schulte, Uwe Tangen
    NGEN: A Massively Parallel Reconfigurable Computer for Biological Simulation: Towards a Self-Organizing Computer. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:260-276 [Conf]
  20. Takayuki Morishita, Iwao Teramoto
    Architecture of Cell Array Neuro-Processor. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:277-288 [Conf]
  21. Tadashi Ae, Hikaru Fukumoto, Saku Hiwatashi
    Special-Purpose Brainware Architecture for Data Processing. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:289-301 [Conf]
  22. Bernard Manderick, Tetsuya Higuchi
    Evolvable Hardware: An Outlook. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:305-311 [Conf]
  23. John R. Koza, Forrest H. Bennett III, David Andre, Martin A. Keane
    Reuse, Parameterized Reuse, and Hierarchical Reuse of Substructures in Evolving Electrical Circuits Using Genetic Programming. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:312-326 [Conf]
  24. Hitoshi Iba, Masaya Iwata, Tetsuya Higuchi
    Machine Learning Approach to Gate-Level Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:327-343 [Conf]
  25. Ricardo Salem Zebulum, Marco Aurélio Cavalcanti Pacheco, Marley B. R. Vellasco
    Evolvable Systems in Hardware Design: Taxonomy, Survey and Applications. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:344-358 [Conf]
  26. Jan Kazimierczak
    From some Tasks to Biology and then to Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:359-376 [Conf]
  27. Masahiro Murakawa, Shuji Yoshizawa, Tetsuya Higuchi
    Adaptive Equalization of Digital Communication Channels Using Evolvable Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:379-389 [Conf]
  28. Adrian Thompson
    An Evolved Circuit, Intrinsic in Silicon, Entwined with Physics. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:390-405 [Conf]
  29. Inman Harvey, Adrian Thompson
    Through the Labyrinth Evolution Finds a Way: A Silicon Ridge. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:406-422 [Conf]
  30. Tomofumi Hikage, Hitoshi Hemmi, Katsunori Shimohara
    Hardware Evolution System Introducing Dominant and Recessive Heredity. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:423-436 [Conf]
  31. Felix A. Gers, Hugo de Garis
    CAM-Brain: A New Model for ATR's Cellular Automata Based Artificial Brain Project. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:437-452 [Conf]
  32. Forrest H. Bennett III, John R. Koza, David Andre, Martin A. Keane
    Evolution of a 60 Decibel Op Amp Using Genetic Programming. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:455-469 [Conf]
  33. Hidenori Sakanashi, Tetsuya Higuchi, Hitoshi Iba, Yukinori Kakazu
    Evolution of Binary Decision Diagrams for Digital Circuit Design Using Genetic Programming. [Citation Graph (0, 0)][DBLP]
    ICES, 1996, pp:470-481 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002