Conferences in DBLP
Laxmi N. Bhuyan , C. W. Lee An Interference Analysis of Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Kumar , J. Robert Jump Generalized Delta Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Doug DeGroot Expanding and Contracting SW-Banyan Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrad Yasrebi , Sanjay R. Deshpande , James C. Browne A Comparison of Circuit Switching and Packet Switching for Data Transfer in Two Simple Image processing Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Efstratios Gallopoulos , S. D. McEwan Numerical Experiments with the Massively parallel Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Loyce M. Adams An M-Step preconditioned Conjugate Gradient Method for Parallel Computation. [Citation Graph (0, 0)][DBLP ] Conf ] John Van Rosendale Minimizing Inner Product Data Dependencies in Conjugate Gradient Iteration. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshiyasu Takefuji , Takakazu Kurokawa , Masato Ishizaki , Hideo Aiso New Matrix Equation Solvers in GF(2) Employing Cramer with Chio Method. [Citation Graph (0, 0)][DBLP ] Conf ] Bharat Deep Rathi , Sanjay R. Deshpande , Matthew Sejnowski , Don Walker , Roy M. Jenevein , G. Jack Lipovski , James C. Browne Specification and Implementation of an Integrated Packet Communication Facility for an Array Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay Dhar , Mark A. Franklin , Donald F. Wann Timing Control of VLSI Based NlogN and Crossbar Networks. [Citation Graph (0, 0)][DBLP ] Conf ] David C. H. Lee , John Paul Shen Easily-Testable (N, K) Shuffle/Exchange Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Padmanabhan , Duncan H. Lawrie Fault Tolerance Schemes in Shuffle-Exchange Type Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Suresh C. Kothari , S. Lakshmivarahan A Condition Known to be Sufficient for Rearrangeability of the Benes Class of Interconnection Networks with 2x2 Switches Is Also Necessary. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Yang Chern , Tadao Murata A Fast Algorithm for Concurrent LU Decomposition and Matrix Inversion. [Citation Graph (0, 0)][DBLP ] Conf ] Qing-Shi Gao , Rong-Quan Wang Vector Computer for Sparse Matrix Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Yang Chern , Tadao Murata Efficient Matrix Multiplications on a Concurrent Data-Loading Array Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Hoshino , Tomonori Shirakawa , Takeshi Kamimura , Takahisa Kageyama , Kiyo Takenouchi , Hidehiko Abe , Satoshi Sekiguchi , Yoshio Oyanagi , Toshio Kawai Highly Parallel Processor Array "PAX" for Wide Scientific Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Doug DeGroot Partitioning Job Structures for SW-Banyan Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Woei Lin , Chuan-lin Wu Configuring Computation Tree Topologies on a Distributed Computing System. [Citation Graph (0, 0)][DBLP ] Conf ] Robert R. Seban , Howard Jay Siegel Performing the Shuffle with the PM2I and Illiac SIMD Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] A. Yavuz Oruç A Classification of Cube-Connected Networks with a Simple Control Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Terrence W. Pratt , Loyce M. Adams , Piyush Mehrotra , John Van Rosendale , Robert G. Voigt , Merrell L. Patrick The FEM-2 Design Method. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeo Sugimoto , Kiyoshi Agusa , Koichi Tabata , Yutaka Ohno A Multi-Microprocessor System for Concurrent LISP. [Citation Graph (0, 0)][DBLP ] Conf ] F. M. Tse A Multi-Micro System for I/O Intensive Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Arumalla V. Reddi Pipeline and Parallel Architectures for Computer Communication Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Krish Purswani , Bijan Jabbari An Interface Message Processor with a Multiprocessing Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Jon G. Kuhl , Sudhakar M. Reddy , P. Raghavan A Class of Graphs for Processor Interconnection. [Citation Graph (0, 0)][DBLP ] Conf ] Karl W. Doty Dense Bus Connection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel A. Reed A Simulation Study of Multimicrocomputer Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Wilson , Daniel P. Siewiorek , Zary Segall Evaluation of Multiprocessor Interconnect Structures with the Cm Testbed. [Citation Graph (0, 0)][DBLP ] Conf ] A. I. Noor , G. S. Hope , O. P. Malik Slot-Based Multi-Access Protocol for Local Computer Network. [Citation Graph (0, 0)][DBLP ] Conf ] Baruch Awerbuch , Tripurari Singh New Connectivity and MSF Algorithms for Ultracomputer and PRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Yung H. Tsin Bridge-Connectivity and Biconnectivity Algorithms for Parallel Computer Models. [Citation Graph (0, 0)][DBLP ] Conf ] Ten-Hwang Lai , Sartaj Sahni Anomalies in Parallel Branch-and-Bound Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph Mohan Experience with Two Parallel Programs Solving the Traveling Salesman Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Danforth DOT, A Distributed Operating System Model of a Tree-Structured Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Peyyun Peggy Li , S. Lennart Johnsson The Tree Machine: An Evaluation of Strategies for Reducing Program Loading Time. [Citation Graph (0, 0)][DBLP ] Conf ] Svetlana P. Kartashev , Steven I. Kartashev Optimal Routing Algorithms in Multicomputer Networks Organized as Reconfigurable Binary Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Quentin F. Stout Sorting, Merging, Selecting, and Filtering on Tree and Pyramid Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Ching C. Hsiao , Lawrence Snyder Omni-sort: A Versatile Data Processing Operation for VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] F. P. Hiner III Pseudo Associative Linking: A High-Speed Searching Algorithm for Parallel Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald H. Perrott , Danny Crookes , Peter Milligan , W. R. Martin Purdy Implementation of an Array and Vector Processing Language. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony P. Reeves , John D. Bruner : A Parallel P-Code for Parallel Pascal and Other High Level Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Nam Sung Woo , Ashok K. Agrawala The DC1 Flow Schema with the Data/Control-Driven Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Yury Litvin Top-Down Data Flow Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Ikram E. Abdou A Pipeline Machine for Image Processing Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Yee-Hong Yang , Tsung-Wei Sze An Evaluation Study of Six Topologies of Parallel Computer Architectures for Scene Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen L. Stepoway , David L. Wells , Gerald R. Kane An Architecture for Efficient Generation of Fractal Surfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Samuel M. Goldwasser , R. A. Reynolds An Architecture for the Real-Time Display and Manipulation of Three-Dimensional Objects. [Citation Graph (0, 0)][DBLP ] Conf ] Edward C. Bronson , Leah H. Jamieson A Parallel Architecture for Labeling, Segmentation, and Lexical Processing in Speech Understanding. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Pierre Finance , M. S. Ouerghi On the Algebraic Specification of Concurrency and Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence Snyder Introduction to the Poker Parallel Programming Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Mancarella , Franco Turini A High Level Analysis Tool for Concurrent Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen J. Allan , R. R. Oldehoeft A Stream Definition for Von Neumann Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Ghassan Z. Qadah , Keki B. Irani A Database Machine for Very Large Relational Databases. [Citation Graph (0, 0)][DBLP ] Conf ] Yang-Chang Hong Efficient Computing of Relational Join Operations by Means of Specialized Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Hungwen Li A VLSI Modular Architecture Methodology for Realtime Signal Processing Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Gerhard Fritsch , W. Kleinoeder , Claus-Uwe Linster , Jens Volkert EMSY85 : The Erlangen Multi-Processor System for a Broad Spectrum of Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jack B. Dennis , Guang R. Gao Maximum Pipelining of Array Operations on Static Data Flow Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Israel Koren , Gabriel M. Silberman A Direct Mapping of Algorithms onto VLSI Processing Arrays Based on the Data Flow Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence Y. Ho , Keki B. Irani An Algorithm for Processor Allocation in a Dataflow Multiprocessing Environment. [Citation Graph (0, 0)][DBLP ] Conf ] William Leler A Small, High-Speed Dataflow Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Prashant S. Sawkar , Timothy J. Forquer , Richard P. Perry Programmable Modular Signal Processor : A Data Flow Computer System for Real-Time Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy S. Axelrod , Paul F. Dubois , Peter G. Eltgroth A Simulation for MIMD Performance Prediction : Application to the S-1 MkIIa Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Avinash Chandak , James C. Browne Vectorization of Discrete Event Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Kang G. Shin , Yann-Hang Lee Analysis of Backward Error Recovery for Concurrent Processes with Recovery Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Ian A. Newman , R. P. Stallard , M. C. Woodward Improved Multiprocessor Garbage Collection Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Trevor N. Mudge , Abdel-Rahman H. Tawil Efficiency of Feature Dependent Algorithms for the Parallel Processing of Images. [Citation Graph (0, 0)][DBLP ] Conf ] Yetung P. Chiang , King-sun Fu Matching Parallel Algorithm and Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce P. Lester Coherent Flow of Information in Parallel Systems. [Citation Graph (0, 0)][DBLP ] Conf ] David Jefferson Virtual Time. [Citation Graph (0, 0)][DBLP ] Conf ] Ruknet Cezzar , David Klappholz Process Management Overhead in a Speedup-Oriented MIMD System. [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth Williams Assigning Processes to Processors in Distributed Systems. [Citation Graph (0, 0)][DBLP ] Conf ] David Lee Tuomenoksa , Howard Jay Siegel Preloading Schemes for the PASM Parallel Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] Bharadwaj Jayaraman Constructing a Parallel Implementation from High-Level Specifications: A Case Study Using Resource Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Thomasian , Paul F. Bay Queueing Network Models for Parallel Processing of Task Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hung-Chang Du , Jean-Loup Baer On the Performance of Interleaved Memories with Non-Uniform Access Probabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Ibrahim H. Önyüksel , Keki B. Irani A Markovian Queueing Network Model for Performance Evaluation of Bus-Deficient Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] I. V. Ramakrishnan , Donald S. Fussell , Abraham Silberschatz On Mapping Homogeneous Graphs on a Linear Array-Processor Model. [Citation Graph (0, 0)][DBLP ] Conf ] Peter R. Cappello , Kenneth Steiglitz Unifying VLSI Array Designs with Geometric Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Peter J. Varman , Donald S. Fussell Design of Robust Systolic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew R. Pleszkun , Edward S. Davidson Structured Memory Access Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. McDowell A Simple Architecture for Low Level Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Takanobu Baba , Katsuhiro Yamazaki , Nobuyuki Hashimoto , Hiroyuki Kanai , Kenzo Okuda , Kazuhiko Hashimoto Hierarchical Micro-Architectures of a Two-Level Microprogrammed Multiprocessor Computer. [Citation Graph (0, 0)][DBLP ] Conf ] J. L. Potter Alternative Data Structures for Lists in Associative Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Martha E. Steenstrup , Daryl T. Lawton , Charles C. Weems Determination of the Rotational and Translational Components of a Flow Field Using a Content Addressable Parallel Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas V. Makam , Cauligi S. Raghavendra Dynamic Relibility Modeling and Analysis of Computer Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Gruia-Catalin Roman , Robert K. Israel Functional Specification of Distributed Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Wong-Hua Lee , Miroslaw Malek MOPAC: A Partitionable and Reconfigurable Multicomputer Array. [Citation Graph (0, 0)][DBLP ] Conf ] Hans-Joerg Brundiers , Richard E. Buehrer , Hansmartin Friess , Milan Tadian The Multiprocessor EMPRESS: A Useful Tool for Studying Parallelization Concepts. [Citation Graph (0, 0)][DBLP ] Conf ] Creve Maples , Daniel Weaver , Douglas Logan , William Rathbun Performance of a Modular Interactive Data Analysis System (MIDAS). [Citation Graph (0, 0)][DBLP ] Conf ] Nikitas J. Dimopoulos The Homogeneous Multiprocessor Architecture : Structure and Performance Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Gajski , David J. Kuck , Duncan H. Lawrie , Ahmed H. Sameh Cedar : A Large Scale Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Clifford N. Arnold Vector Optimization on the CYBER 205. [Citation Graph (0, 0)][DBLP ] Conf ] Lionel M. Ni , Kai Hwang Pipelined Evaluation of First-Order Recurrence Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Wilfried Oed , Otto Lange The Solution of Linear Recurrence Relations on Pipelined Processors. [Citation Graph (0, 0)][DBLP ] Conf ] John Robert Burger Data-Stationary Instructions as a Way to Minimize Long Distance Communications in VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] 