Conferences in DBLP
Dror G. Feitelson , Larry Rudolph Mapping and Scheduling in a Shared Parallel Environment Using Distributed Hierarchical Control. [Citation Graph (0, 0)][DBLP ] Conf ] Gilbert C. Sih , Edward A. Lee Scheduling to Account for Interprocessor Communication within Interconnection-Constrained Processor Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jiahuang Ji , Menkae Jeng Dynamic Task Allocation on Shared Memory Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ramaswamy Venkatesh , Galigekere R. Dattatreya Adaptive Optimal Load Balancing of Loosely Coupled Processors with Arbitrary Service Time Distributions. [Citation Graph (0, 0)][DBLP ] Conf ] Josep Torrellas , John L. Hennessy Estimating the Performance Advantages of Relaxing Consistency in a Shared Memory Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew T. O'Keefe , Henry G. Dietz Hardware Barrier Synchronization: Static Barrier MIMD (SBM). [Citation Graph (0, 0)][DBLP ] Conf ] Matthew T. O'Keefe , Henry G. Dietz Hardware Barrier Synchronization: Dynamic Barrier MIMD (DBM). [Citation Graph (0, 0)][DBLP ] Conf ] Sarita V. Adve , Mark D. Hill Implementing Sequential Consistency in Cache-Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Schwederski , Howard Jay Siegel , Thomas L. Casavant Optimizing Task Migration Transfers Using Multistage Cube Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Mingfang Wang , Behrooz Shirazi Round-Robin Load Balancing in a Shared Memory Multiprocessor System. [Citation Graph (0, 0)][DBLP ] Conf ] Lal George A Scheduling Strategy for Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna P. Belkhale , Prithviraj Banerjee An Approximate Algorithm for the Partitionable Independent Task Scheduling Problem. [Citation Graph (2, 0)][DBLP ] Conf ] C. S. Raghavendra , Rajendra V. Boppana On Methods for Fast and Efficient Parallel Memory Access. [Citation Graph (0, 0)][DBLP ] Conf ] Mark A. Nichols , Howard Jay Siegel , Henry G. Dietz , Russell W. Quong , Wayne G. Nation Minimizing Memory Requirements for Partitionable SIMD/SPMD Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Charles Severance , Sakti Pramanik Distributed Linear Hashing for Main Memory Databases. [Citation Graph (0, 0)][DBLP ] Conf ] Forbes J. Burkowski , Gordon V. Cormack Use of Perfect Hashing in a Paged Memory Management Unit. [Citation Graph (0, 0)][DBLP ] Conf ] Weijia Shang , José A. B. Fortes Time-Optimal and Conflict-Free Mappings of Uniform Dependence Algorithms into Lower Dimensional Processor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Zhimin Tang , Guo-Jie Li Optimal Granularity of Grid Iteration Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Keqin Li , Kam-Hoi Cheng Job Scheduling in PMCS Using a 2DBS as the System Partitioning Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] K. J. Ray Liu , Kung Yao Multi-Phase Systolic Architectures for Spectral Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Arun K. Thakore , Stanley Y. W. Su , Herman Lam , Dennis G. Shea Asynchronous Parallel Processing of Object Bases Using Multiple Wavefronts. [Citation Graph (0, 0)][DBLP ] Conf ] Flavio De Paoli , Mehdi Jazayeri Development of a Partitioned, Replicated Data Server in FLAME. [Citation Graph (0, 0)][DBLP ] Conf ] Kiyoshi Nakabayashi A Bus-Connected Multiprocessor for Run-Length-Based Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Khaled M. Elleithy , Magdy A. Bayoumi Formal Synthesis of a Parallel Architectures from Recursive Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Edward W. Davis , Joann M. Jennings Evaluation of New Architectural Features in a Massively Parallel SIMD Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Anastasios A. Economides , Michel Dubois Transient Models of Bus-Based Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Arun K. Nanda , Honda Shing , Ten H. Tzen , Lionel M. Ni A Replicate Workload Framework to Study Performance Degradation in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Tein Y. Chung , Dharma P. Agrawal Cost-Performance Tradeoffs in Manhattan Street Network versus 2-D Torus. [Citation Graph (0, 0)][DBLP ] Conf ] Syed Masud Mahmud , Venkat Tiruveedhula Hit Ratio and Communication Cost of Shared Data in a Cache-Based System with Multistage Interconnection Network. [Citation Graph (0, 0)][DBLP ] Conf ] Anup Kumar , Dharma P. Agrawal On System Effectiveness Evaluation of Real-Time Parallel and Distributed Computing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Samuel Ho , Lawrence Snyder A Formal Model of the Processor Memory Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Thin-Fong Tsuei , Mary K. Vernon Diagnosing Parallel Program Speedup Limitations Using Resource Contention Models. [Citation Graph (0, 0)][DBLP ] Conf ] Lance Kurisaki , Tomás Lang The Performance of a Faulty Multistage Interconnection Network with Diverting Switches and Correction Links. [Citation Graph (0, 0)][DBLP ] Conf ] Javaid Aslam On Designing Hardware-Efficient Parallel Architectures for the Class NC. [Citation Graph (0, 0)][DBLP ] Conf ] Lishing Liu , Jih-Kwon Peir A Performance Evaluation Methodology for Coupled Multiple Supercomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph JáJá , Kwan Woo Ryu Load Balancing on the Hypercube and Related Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Hao Huang , Jie-Yong Juang A Partial Compaction Scheme for Processor Allocation in Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Shahram Latifi The Efficiency of the Folded Hypercube in Subcube Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Frank J. Weil , Leah H. Jamieson , Edward J. Delp An Analysis of Fixed-Assignment Hypercube Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Sotirios G. Ziavras Techniques for Mapping Deterministic Algorithms onto Multi-Level Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin W. Wah , Lon-Chan Chu Optimal Mapping of Neural Networks on Multicomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Weicheng Shen Parallel Architectures for a Class of Neural Net Based Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Konstantinos I. Diamantaras , David L. Heine , Isaac D. Scherson Implementation of Neural Network Algorithms on the P3 Parallel Associative Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Shu-Chin Wang , Yeh-Hao Chin , Kuo-Qin Yan Reaching a Fault Detection Agreement. [Citation Graph (0, 0)][DBLP ] Conf ] Nageswara S. V. Rao On Parallel Algorithms for Single-Fault Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] Alireza Kavianpour , K. H. Kim Diagnostic Power of Four Basic System-Level Diagnosis Strategies for Hypercubes. [Citation Graph (0, 0)][DBLP ] Conf ] Junsheng Long , W. Kent Fuchs , Jacob A. Abraham Forward Recovery Using Checkpointing in Parallel Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Tien Ho Full Bandwidth Communications for Folded Hypercubes. [Citation Graph (0, 0)][DBLP ] Conf ] Sivarama P. Dandamudi A Performance Comparison of Routing Algorithms for Hierarchical Hypercube Multicomputer Networks. [Citation Graph (0, 0)][DBLP ] Conf ] C. S. Raghavendra , M. A. Sridhar Optimal Routing of Bit-Permutes on Hypercube Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Sivarama P. Dandamudi , Derek L. Eager The Effectiveness of Combining in Reducing Hot-Spot Contention in Hypercube Multicomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Ted H. Szymanski A Comparison of Circuit and Packet Switching in a Fiber-Optic Hypercube. [Citation Graph (0, 0)][DBLP ] Conf ] Yahui Zhu , Mohan Ahuja Preemptive Job Scheduling on a Hypercube. [Citation Graph (0, 0)][DBLP ] Conf ] Sang Lyul Min , Jean-Loup Baer A Performance Comparison of Directory-based and Timestamp-based Cache Coherence Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Anoop Gupta , Wolf-Dietrich Weber , Todd C. Mowry Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip B. Gibbons Cache Support for the Asynchronous PRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Abraham Mendelson , Dominique Thiébaut , Dhiraj K. Pradhan Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Barry G. Douglass , A. Yavuz Oruç Self-Routing and Route Balancing in Connection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Calvin J. A. Hsia , C. Y. Roger Chen Permutation Capability of Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Robert A. Rowley , Bella Bose On Necklaces in Shuffle-Exchange and de Bruign Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen K. Wysham , Tse-Yun Feng On Routing a Faulty Benes Network. [Citation Graph (0, 0)][DBLP ] Conf ] Kanad Ghose , Kiran Raghavendra Desai The Design and Evaluation of the Hierarchical Cubic Network. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Padmanabhan A Generalization of the Binary Shuffle-Exchange Architecture for Non-Power-of-Two System Sizes. [Citation Graph (0, 0)][DBLP ] Conf ] Sang-Bang Choi , Arun K. Somani The Generalized Folding-Cube. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth E. Batcher On Bitonic Sorting Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Isaac D. Scherson Orthogonal Graphs and the Analysis and Construction, of a Class of Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Franks , Bruce M. McMillin , Rashi Khanna PAFMV-Pairwise Asynchronous Multigrid. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Shyen E. Chen , Kyungsook Y. Lee , Ming T. Liu U-Star: A Modular Indirect Star Network Based on (2 X 2) Switches. [Citation Graph (0, 0)][DBLP ] Conf ] Barry G. Douglass A New Class of Three-Stage Switching Networks and Their Routing Properties. [Citation Graph (0, 0)][DBLP ] Conf ] Robert L. Lesher , Matthew Thazhuthaveetil Hotspot Contention in Non-Blocking Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Paraskevas Evripidou , Jean-Luc Gaudiot A Decoupled Graph/Computation Data-Driven Architecture with Variable-Resolution Actors. [Citation Graph (0, 0)][DBLP ] Conf ] Ali R. Hurson , Ben Lee , Behrooz Shirazi , Mingfang Wang A Program Allocation Scheme for Data Flow Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Suresh Chittor , Richard J. Enbody Performance Degradation in Large Wormhole-Routed Interprocessor Communication Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Richard J. Lipton , Dimitrios N. Serpanos Uniform-Cost Communication in Scalable Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Nian-Feng Tzeng , Sourav Bhattacharya , Po-Jen Chuang Fault-Tolerant Cube-Connected Cycles Structures Through Dimensional Substitution. [Citation Graph (0, 0)][DBLP ] Conf ] Hideharu Amano A Fault Tolerant Batcher Network. [Citation Graph (0, 0)][DBLP ] Conf ] Mazin S. Algudady , Chita R. Das , Woei Lin Fault-Tolerant Task Mapping Algorithms for MIN-Based Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Hussein M. Alnuweiri A New Class of Optimal VLSI Networks for Multidimensional Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Azer Bestavros SETH: A VLSI Chip for the Real-Time Information Dispersal and Retrieval for Security and Fault-Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Hsien-Fen Hsieh , Shing-Tsaan Huang , Su-Chu Hsu A Linear Systolic Algorithm for Finding Bridges on an Undirected Connected Graph. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. Stroud , Ahmed E. Barbour Parallel Processing and Hardware Acceleration for Synthesis of VLSI Devices from Behavioral Models. [Citation Graph (0, 0)][DBLP ] Conf ] Dan I. Moldovan , Wing Lee , Changwa Lin , Sang-Hwa Chung Parallel Knowledge Processing on SNAP. [Citation Graph (0, 0)][DBLP ] Conf ] Jun-Tae Kim , Dan I. Moldovan Parallel Knowledge Classification on SNAP. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel P. Miranker , Archie D. Andrews On Balanced Synchronous Parallel Computers for AI. [Citation Graph (0, 0)][DBLP ] Conf ] Alok N. Choudhary , Janak H. Patel Performance Evaluation of Clusters of NETRA: An Architecture for Computer Vision Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Wiljo J. van Beek , Rob A. H. Twist , Marnix C. Vlot Evaluation of the Communication Network of POOMA. [Citation Graph (0, 0)][DBLP ] Conf ] Jiun-Ming Hsu , Prithviraj Banerjee Hardware Support for Message Routing in a Distributed Memory Multicomputer. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen A. Mabbs , Kevin E. Forward Optimizing the Communication Architecture of a Hierarchical Parallel Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Seth Abraham , Krishnan Padmanabhan Constraint Based Evaluation of Multicomputer Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Maya Gokhale , William Holmes , Andrew Kopser , Dick Kunze , Daniel P. Lopresti , Sara Lucas , Ronald Minnich , Peter Olsen SPLASH: A Reconfigurable Linear Logic Array. [Citation Graph (0, 0)][DBLP ] Conf ] Robert W. Horst Task Flow Computer Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Isaac D. Scherson , David A. Kramer , Brian D. Alleyne A Fine-Grain Bit-Parallel, Word-Parallel, Massively-Parallel Associative Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Behrooz Parhami Systolic Associative Memories. [Citation Graph (0, 0)][DBLP ] Conf ] David R. Barach , Robert Wells , Thomas Uban , James Gibson Highly Parallel Virtual Memory Management on the TC2000. [Citation Graph (0, 0)][DBLP ] Conf ] Min-You Wu , Wei Shu A Dynamic Partitioning Strategy on Distributed Memory Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Eugene D. Brooks III , Joseph E. Hoag A Scalable Coherent Cache System With Incomplete Directory State. [Citation Graph (0, 0)][DBLP ] Conf ] Michael W. Strevell , Harvey G. Cragon Data Type Coherency in Heterogeneous Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Waldecker , Mario J. Gonzalez Jr. Reliability in Bus Structured and Completely Connected Distributed Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Salim Hariri , A. Gaber Mohamed , Hasan B. Mutlu Modeling Availability of Parallel Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff D. Martens , D. N. Jayasimha A Tree Structured Hierarchical Memory Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] David J. Lilja , Pen-Chung Yew Comparing Parallelism Extraction Techniques: Superscalar Processors, Pipelined Processors, and Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Tein-Hsiang Lin , Adly T. Fam A Hierarchical Approach for the Design of Two-Dimensional Fault-Tolerant Systolic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Nishikawa , Kazuo Sakushima , Takashi Hamada , Motohiro Misawa , Katsura Kawakami Grain Size Oriented Pipeline Machine - GRAPE. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Willebeek-LeMair , Anthony P. Reeves Local v Global Strategies for Dynamic Load Balancing. [Citation Graph (0, 0)][DBLP ] Conf ] Swie-Tsing Tan , David Hung-Chang Du On Subcube Allocation and Relinquishment Schemes for Hypercube Connected Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Win-Tsung Lo , Satish K. Tripathi , Dipak Ghosal Task Allocation on the Hypercube Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Emilio Luque , Ana Ripoll , Porfidio Hernández , Tomàs Margalef Task Duplication Static-Scheduling for Multiprocessor Systems with Non-Fixed Execution Time Tasks. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenqiang Fan , Kam-Hoi Cheng A Data Flow Architecture Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Dikran S. Meliksetian , C. Y. Roger Chen Communication Aspects of the Cube Connected Cycles. [Citation Graph (0, 0)][DBLP ] Conf ] Abdou Youssef , Bruce W. Arden Structure of Digit Permutation Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Shyh-Kwei Chen n+ ^-Cube: The Extra Dimensional n-Cube. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard L. Menezes , Ramakrishna Thurimella Reliability Analysis of Two Classes of Double-Tree Network-Based Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Wohl , Thomas W. Christopher SIMD Neural Net Mapping on MIMD Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyong Liu , Jia-Huai You Finding the Shortest Path in ESMSS Network. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid R. Arabnia A Multi-Ring Transputer Network for the Arbitrary Rotation of Raster Images. [Citation Graph (0, 0)][DBLP ] Conf ] Won S. Lee , Rangasami L. Kashyap , Phillip C.-Y. Sheu On Optimal Evaluation of Conjunctive Queries in Parallel Environments. [Citation Graph (0, 0)][DBLP ] Conf ] Reza Hashemian Parallel Addition Using Pipeline Structure. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenqiang Fan , Kam-Hoi Cheng A Generalized Simultaneous Access Dictionary Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Gu , Rok Sosic A Parallel Optimal Arc Consistency Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Mahdi Abdelguerfi , H. Munaf A Bit-Sliced Special Purpose Unit for Relational Database Aggregation Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Yaohon Chu , Kozo Itano Coprocessor Parallel Architecture for Compilation. [Citation Graph (0, 0)][DBLP ] Conf ] Nimish R. Shah , Lalit M. Patnaik SPARCS: A System for Parallel Architecture Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Aloke Guha A Fine-Grained Parallel Architecture for Graph Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein , Alexander G. Hirschbiel , M. Weber The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Butler , Yale N. Patt An Area-Efficient Register Alias Table for Implementing HPS. [Citation Graph (0, 0)][DBLP ] Conf ] Katsuto Nakajima , Nobuyuki Ichiyoshi Evaluation of Inter-processor Communication in the KL1 Implementation on the Multi-PSI. [Citation Graph (0, 0)][DBLP ] Conf ] Michael A. Young Livermore Loops on the Connection Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Jean Frédéric Myoupo A Linear Systolic Array for Transitive Closure Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Irving S. Reed , Xuemin Chen , Trieu-Kien Truong An Integral Microcontroller Architecture Designed by Using the Register Transfer Language for VLSI Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay P. Kumar , S. J. Wang Dynamic Full Access in Fault Tolerant Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] 