Conferences in DBLP
Zhixi Fang , Peiyi Tang , Pen-Chung Yew , Chuan-Qi Zhu Dynamic Processor Self-Scheduling for General Parallel Nested Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Zhixi Fang , Peiyi Tang , Pen-Chung Yew , Chuan-Qi Zhu Deadlock Prevention in Processor Self-Scheduling for Parallel Nested Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Ron Cytron , Jeanne Ferrante What's In a Name? -or- The Value of Renaming for Parallelism Detection and Storage Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Roland L. Lee , Pen-Chung Yew , Duncan H. Lawrie : Data Prefetching In Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Walid A. Najjar , Jean-Luc Gaudiot Multi-Level Execution In Data-Flow Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen A. Brobst Organization of an Instruction Scheduling and Token Storage Unit in a Tagged Token Dataflow Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Makoto Amamiya A New Parallel Graph Reduction Model and Its Machine Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Sener Ilgen , Isaac D. Scherson Parallel Processing on VLSI Associative Memory. [Citation Graph (0, 0)][DBLP ] Conf ] R. D. Rasmussen , G. S. Bolotin , Nikitas J. Dimopoulos , B. F. Lewis , R. M. Manning Advanced General Purpose Multicomputer for Space Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sudarshan K. Dhall , S. Lakshmivarahan , Chi-Ming Yang On a New Class of Optimal Parallel Prefix Circuits with (Size+Depth) = 2n-2 AND\lceil log n \rceil DEPTH(2 \lceil log n \rceil -3). [Citation Graph (0, 0)][DBLP ] Conf ] Albert G. Greenberg , Boris D. Lubachevsky Simple, Efficient Asynchronous Parallel Prefix Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Champion , Jerome Rothstein Immediate Parallel Solution of the Longest Common Subsequence Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth Edmiston , Robert A. Wagner Parallelization of the Dynamic Programming Algorithm for Comparison of Sequences. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas J. LeBlanc , Sanjay Jain Crowd Control: Coordinating Processes in Parallel. [Citation Graph (0, 0)][DBLP ] Conf ] P. G. McGuire , Ravishankar K. Iyer A Measurement-Based Study of Concurrency in a Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Masud Rahgozar , Colette Rolland A Proposal for Optimization of Distributed Concurrency Control. [Citation Graph (0, 0)][DBLP ] Conf ] D. N. Jayasimha Parallel Access to Synchronization Variables. [Citation Graph (0, 0)][DBLP ] Conf ] Jungbae H. Kim , Sridhar Reddy Adnapally On Easily Testable and Reconfigurable Two-Dimensional Systolic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Derek C. W. Pao , Hon F. Li , R. Jayakumar Dynamic Reconfiguration for Fault-Tolerant Systolic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] David L. Landis , Daniel C. Muha , William A. Check Influence of Built-In Self Test on the Performance of Fault Tolerant VLSI Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Yuval Tamir , Eli Gafni A Software-Based Hardware Fault Tolerance Scheme for Multicomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chian Yang , John A. Silvester Graceful Degradation of Fault Tolerant Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jit Biswas , James C. Browne Simultaneous Update of Priority Structures. [Citation Graph (0, 0)][DBLP ] Conf ] Eliezer Dekel , Simeon C. Ntafos , Shietung Peng Compression Trees and Their Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sakti Pramanik , Myoung-Ho Kim HCB-Tree: A B-Tree Structure for Parallel Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Abimbola O. Oshisanwo , Paul P. Dasiewicz A Parallel Model and Architecture for Production Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rasiah Loganantharaj Parallel Link Resolution of Connection Graph Refutation and Its Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Deborah Knox , Charles T. Wright Combinators as Control Mechanisms in Multiprocessing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Nam Sung Woo , Ramautar Sharma An AND-OR Parallel Execution System for Logic Program Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Franz Schreiner , Gerhard Zimmermann PESA I-A Parallel Architecture for Production Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hee Yong Youn , Adit D. Singh On Area Efficient and Fault Tolerant Tree Embedding In VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Y. W. Eva Ma , Lixin Tao Embeddings Among Toruses and Meshes. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Tien Ho , S. Lennart Johnsson On the Embedding of Arbitrary Meshes in Boolean Cubes With Expansion Two Dilation Two. [Citation Graph (0, 0)][DBLP ] Conf ] P. Sadayappan , Fikret Erçal , Steven Martin Mapping Finite Element Graphs onto Processor Meshes. [Citation Graph (0, 0)][DBLP ] Conf ] I. Arieh Cimet , Srikanta P. R. Kumar A Resilient Distributed Algorithm for Minimum-Weight Spanning Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Shaunak Pawagi Parallel Algorithm for Maximum Weight Matching in Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Gopal Lakhani , R. Dorairaj A VLSI Implementation of All-Pair Shortest Path Problem. [Citation Graph (0, 0)][DBLP ] Conf ] An-Chi Liu , Y. M. Zou , Der-Ming Liou Divide and Conquer for a Shortest Path Problem. [Citation Graph (0, 0)][DBLP ] Conf ] John M. Marberg , Eli Gafni An O(n^2 m^1/2) Distributed Max-Flow Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Jih-Kwon Peir , Ron Cytron Minimum Distance: A Method for Partitioning Recurrences for Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Ron Cytron Limited Processor Scheduling of Doacross Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Constantine D. Polychronopoulos Loop Coalesing: A Compiler Transformation for Parallel Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Santosh G. Abraham , Janak H. Patel Parallel Garbage Collection on a Virtual Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] Alan Norton , Evelyn Melton A Class of Boolean Linear Transformations for Conflict-Free Power-of-Two Stride Access. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Dubois Effect of Invalidations on the Hit Ratio of Cache-Based Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Loup Baer , Wen-Hann Wang Architectural Choices for Multi-level Cache Hierarchies. [Citation Graph (0, 0)][DBLP ] Conf ] David R. Emberson A Cache Coherence Management Technique for Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Donald C. Winsor , Trevor N. Mudge Crosspoint Cache Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] John H. Reif , Sandeep Sen Optimal Randomized Parallel Algorithms for Computational Geometry. [Citation Graph (0, 0)][DBLP ] Conf ] Virendra K. Janakiram , Dharma P. Agrawal , Ravi Mehrotra Randomized Parallel Algorithms for Prolog Programs and Backtracking Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Russ Miller , Quentin F. Stout Mesh Computer Algorithms for Line Segments and Simple Polygons. [Citation Graph (0, 0)][DBLP ] Conf ] T. Hari Krishna Prasad , C. Pandurangan New Parallel Algorithms for the Maximum Empty Rectangle Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Tony DeRose , Lawrence Snyder , Chyan Yang Near-Optimal Speedup of Graphics Algorithms Using Multigauge Parallel Computers. [Citation Graph (0, 0)][DBLP ] Conf ] David Callahan , Ken Kennedy , John Cocke Estimating Interlock and Improving Balance for Pipelined Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Maya Gokhale Exploiting Loop Level Parallelism in Nonprocedural Dataflow Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Byler , Michael Wolfe , James R. B. Davies , Christopher Huson , Bruce Leasure Multiple Version Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Nishikawa , Hiroaki Terada , Kohji Komatsu , Shin-ichi Yoshida , Toshiya Okamoto , Yoshiko Tsuji , Saki Takakura , Tsuyoshi Tokura , Yoichiro Nishikawwa , Shuji Hara , Mitsuo Meichi Architecture of a One-Chip Data Driven Processor: Q-p. [Citation Graph (0, 0)][DBLP ] Conf ] Katsuhiko Asada , Hiroaki Terada , Satoshi Matsumoto , Souichi Miyata , Hajime Asano , Hiroki Miura , Masahisa Shimizu , Shinji Komori , Takeshi Fukuhara , Kenji Shima Hardware Structure of a One-Chip Data Driven Processor: Q-p. [Citation Graph (0, 0)][DBLP ] Conf ] Herman Lam , Stanley Y. W. Su , F. L. C. Seeger , William R. Eisenstadt A Special Function Unit for Database Operations Within a Data-Control Flow System. [Citation Graph (0, 0)][DBLP ] Conf ] Paul T. Hulina , Lee D. Coraor A Hardware Memory Mapping Unit for Efficient Address Computation. [Citation Graph (0, 0)][DBLP ] Conf ] André Seznec , Yvon Jégou Optimizing Memory Throughput In a Tightly Coupled Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Nicol , Frank H. Willard Problem Size, Parallel Architecture, and Optimal Speedup. [Citation Graph (0, 0)][DBLP ] Conf ] Guy E. Blelloch Scans as Primitive Parallel Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Gen-Huey Chen , Maw-Sheng Chern Designing Parallel Algorithms from Regular Graphs and Semi-Regular Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Livny , Udi Manber Active Channels and Their Applications to Parallel Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Mario Barbacci , Jeannette M. Wing DURRA : A Task-Level Description Language. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Eicholz Parallel Programming with ParMod. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Bisiani , Alessandro Forin Multilanguage Parallel Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony P. Reeves , Donna Bergmark Parallel Pascal and the FPS Hypercube Supercomputer. [Citation Graph (0, 0)][DBLP ] Conf ] Doug Baldwin , Cesar Quiroz Parallel Programming and the CONSUL Language. [Citation Graph (0, 0)][DBLP ] Conf ] Sheldon B. Akers , Balakrishnan Krishnamurthy , Dov Harel The Star Graph: An Attractive Alternative to the n-Cube. [Citation Graph (0, 0)][DBLP ] Conf ] M. A. Sridhar , C. S. Raghavendra Uniform Minimal Full-Access Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Daeshik Lee The Lambda Network: A New Permutation Network. [Citation Graph (0, 0)][DBLP ] Conf ] Hungwen Li , Massimo Maresca Polymorphic-Torus Network. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Mandell Experiences and Results Multitasking a Hydrodynamics Code on Global and Local Memory Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Virendrakumar C. Bhavsar , T. Tassou , Esam M. A. Hussein , Kyle A. Gallivan Monte Carlo Neutron Transport on the Alliant FX/8. [Citation Graph (0, 0)][DBLP ] Conf ] Raad A. Fatoohi , Chester E. Grosch Implementation of a Four Color Cell Relaxation Scheme on the MPP, Flex/32 and CRAY/2. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Barszcaz , Lauri S. Howard Static Data Flow Simulation Study at Ames Research Center. [Citation Graph (0, 0)][DBLP ] Conf ] James M. Purtilo , Daniel A. Reed , Dirk Grunwald Environments for Prototyping Parallel Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Terrence W. Pratt The Pisces 2 Parallel Programming Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Brandes , Manfred Sommer A Knowledge Based Parallelization Tool in a Programming Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce Martin , Charles Bergan , Brian Russ PARPC : A System for Parallel Procedure Calls. [Citation Graph (0, 0)][DBLP ] Conf ] Alain Jean-Marie Re-Routing and Resequencing in Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Israel Gazit , Miroslaw Malek On the Number of Permutations Performable by Extra-Stage Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Simin H. Pakzad Fault Tolerance Analysis of Rearrangeable Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Zhixi Fang , Jitender S. Deogun A Heuristic Algorithm for Conflict Resolution Problem Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Abhiram G. Ranade , S. Lennart Johnsson The Communication Efficiency fo Meshes, Boolean Cubes and Cube Connected Cycles for Wafer Scale Integraton. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy A. Davis , Edward S. Davidson PSOLVE : A Concurrent Algorithm for Solving Sparse Systems of Linear Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Gerard G. L. Meyer , Louis J. Podrazik Parallel Implementations of Gradient Based Iterative Algorithms for a Class of Discrete Optimal Control Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Armstrong Optimization of Householder Transformations Part I: Linear Least Squares. [Citation Graph (0, 0)][DBLP ] Conf ] Aydin Üresin , Michel Dubois Asynchronous Relaxation of Non-Numerical Data. [Citation Graph (0, 0)][DBLP ] Conf ] Carla Schlatter Ellis , Thomas J. Olson Parallel First Fit Memory Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Hai-Bo Chen , Yun-Gui Ci Parallel Execution of Non-Do Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Erik H. D'Hollander , Johan Opsommer Implementation of An Automatic Program Partitioner on a Homogeneous Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Charles Koelbel , Piyush Mehrotra , John Van Rosendale Semi-Automatic Domain Decomposition in BLAZE. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas H. Cormen Efficient Multichip Partial Concentrator Switches. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok K. Adiga , Sanjay R. Deshpande Evaluation of Effectivenesss of Circuit Based and Packet Based Interconnection Networks Via Petri Net Models. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunsoo Yoon , Kyungsook Y. Lee , Ming T. Liu Performance Analysis and Comparison of Packet Switching Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Ding-Zhu Du , Frank K. Hwang , Andrew M. Odlyzko , Yanjun Zhang Minimal-Distance Routing for Kykios II. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Y. H. Chuang , Ling Chen A Fixed Size Systolic Array for Arbitrarily Large Eigenvalue Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Chang Nian Zhang , Behrooz Shirazi , David Y. Y. Yun Parallel Designs for Chinese Remainder Conversion. [Citation Graph (0, 0)][DBLP ] Conf ] Rami G. Melhem Iterative Solution of Sparse Linear Systems on Systolic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando J. Nuñez , Núria Torralba Transitive Closure Partitioning and Its Mapping to a Systolic Array. [Citation Graph (0, 0)][DBLP ] Conf ] Howard B. Coleman The Vectorizing Compiler for the Unisys ISP. [Citation Graph (0, 0)][DBLP ] Conf ] Neal M. Gafter Algorithms and Data Structures for Parallel Incremental Parsing. [Citation Graph (0, 0)][DBLP ] Conf ] Dilip Sarkar , Narsingh Deo An Optimal Parallel Parsing Algorithm for a Class of Block Structured Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Y. N. Srikant Parallel Parsing of Arithmetic Expressions. [Citation Graph (0, 0)][DBLP ] Conf ] Nikitas J. Dimopoulos , Kin F. Li , Eric Chi-Wah Wong , R. V. Dantu , J. William Atwood The Homogeneous Multiprocessor System, An Overview. [Citation Graph (0, 0)][DBLP ] Conf ] W. J. Jager , Wayne M. Loucks The P-MACHIne : A Hardware Message Accelerator for a Multiprocessor System. [Citation Graph (0, 0)][DBLP ] Conf ] Shahram Barkhordarian RAMPS: A Realtime Structured Small-Scale Data Flow System for Parallel Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Anderson , Francine Berman Removing Useless Tokens from a Dataflow Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Rudy Lauwereins , J. A. Peperstraete An Integrated Software-Hardware Multiprocesor Project. [Citation Graph (0, 0)][DBLP ] Conf ] S. Lennart Johnsson , Ching-Tien Ho Algorithms for Matrix Transposition on Boolean n-Cube Configured Ensemble Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Youngju Won , Sartaj Sahni Maze Routing on a Hypercube Multiprocessor Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Russ Miller , Susan E. Miller Using Hypercube Multiprocessors to Determine Geometric Properties of Digitized Pictures. [Citation Graph (0, 0)][DBLP ] Conf ] Cevdet Aykanat , Füsun Özgüner Large Grain Parallel Conjugate Gradient Algorithms on a Hypercube Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Bradley R. Engstrom , Peter R. Cappello The SDEF Systolic Programming System. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony Bolmarcich , Kimming So , Frederica Darema , V. Alan Norton A Speedup Analyzer for Parallel Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Rhys S. Francis , Ian D. Mathieson An Evaluation of Parallel Procedure Calls. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce P. Lester , Gregory R. Guthrie A System for Investigating Parallel Algorithm and Architecture Interaction. [Citation Graph (0, 0)][DBLP ] Conf ] William W. Carlson , José A. B. Fortes On the Performance of Combined Data Flow and Control Flow Systems: Experiments Using Two Iterative Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Dipak Ghosal , Laxmi N. Bhuyan Performance Analysis of the MIT Tagged Token Dataflow Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Steven D. Kugelmass , Kenneth Steiglitz , Richard K. Squier Performance of VLSI Engines for Lattice Computations. [Citation Graph (0, 0)][DBLP ] Conf ] Umakishore Ramachandran , Marvin H. Solomon , Mary K. Vernon Techniques for Reducing the Complexity of Large System Models. [Citation Graph (0, 0)][DBLP ] Conf ] Wlodzimierz M. Zuberek Timed Petri Nets in Modelling and Evaluation of Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jong Lee , Sartaj Sahni , Eugene Shragowitz A Hypecube Algorithm for the 0/1 Knapsack Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Amos Omondi , J. Dean Brock Implemnting a Dictionary on Hypercube Machines. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Poplawski , David O. Rich Code Paging on Hypercubes. [Citation Graph (0, 0)][DBLP ] Conf ] Jing-Fu Jenq , Sartaj Sahni All Pairs Shortest Paths on a Hypercube Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Ta King , Lionel M. Ni , Phillip Prins Parallel Algorithm Design Considerations for Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Todd R. Allen , David A. Padua Debugging Parallel Fortran on a Shared Memory Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur P. Goldberg , David R. Jefferson Transparent Process Cloning: A Tool for Load Management of Distributed Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Alfred Hough , Janice E. Cuny Belvedere: Prototype of a Pattern Oriented Debugger for Highly Parallel Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel A. Reed , Allen D. Malony , Patrick J. McGuire MPF: A Portable Message Passing Facility for Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Yoram Eisenstadter , Gerald Q. Maguire Jr. Exploiting Locality of Reference in MIMD Parallel Symbolic Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Moon-Jung Chung , Bala Ravikumar Bounds on the Size of Test Sets for Sorting and Related Networks. [Citation Graph (0, 0)][DBLP ] Conf ] M. A. Sridhar Testing Permutation Network Equivalence. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Cherkassky A Coding Scheme for Concurrent Error Detection/Correction In Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Insup Lee , David Smitley Synthesis of Topologies with Minimum Total Expansion. [Citation Graph (0, 0)][DBLP ] Conf ] A. Yavuz Oruç , Ajai Thirumalai Cellular Permutation Network Designs with Coset Generators. [Citation Graph (0, 0)][DBLP ] Conf ] Viktor K. Prasanna , Venkatesh Krishnan Efficient Image Template Matching on Hypercube SIMD Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Cypher , Jorge L. C. Sanz , L. Snyder Practical Algorithms for Image Component Labeling on SIMD Mesh Connected Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Jik H. Chang , Oscar H. Ibarra , Ting-Chuen Pong , Stephen M. Sohn Two-Dimensional Convolution on a Pyramid Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Ajit Agrawal , Lena Nekludova , Willie Lim A Parallel O(log N) Algorithm for Finding Connected Components In Planar Images. [Citation Graph (0, 0)][DBLP ] Conf ] Yifong Shih , Keki B. Irani Large Scale Unification Using a Mesh-Connected Array of Hardware Unifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Arvind K. Bansal , Leon Sterling On Source-To Source Transformation of Sequentlal Logic Programs to And-Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Tsuen Chen , Kuen-Rong Hseih An Overlapping Unification Algorithm and its Hardware Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip C.-Y. Sheu Pipelined Evaluation of Conjunctive Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Hwang , Joydeep Ghosh Hypernet Architectures for Parallel Processing. [Citation Graph (0, 0)][DBLP ] Conf ] William Tsun-Yuk Hsu , Chuan-Qi Zhu , Pen-Chung Yew An Enhancement Scheme for Hypercube Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] A. Yavuz Oruç Multistage Permutation Network Design with Double Coset Generators. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad M. Jrad , Richard W. Hall Orthogonal Fast Channels: An Enhanced Mesh Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Frank K. H. A. Dehne , Nicola Santoro Optimal VLSI Dictionary Machines on Meshes. [Citation Graph (0, 0)][DBLP ] Conf ] S. Purushothaman Reasoning About Modular Systolic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Nikrouz Faroughi , Michael A. Shanblatt Systematic Generation and Enumeration of Systolic Arrays from Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Peter J. Varman , Kshitij Doshi Determining Biconnectivity on a Systolic Array. [Citation Graph (0, 0)][DBLP ] Conf ] Katherine M. Baumgartner , Benjamin W. Wah Load Balancing Protocols on a Local Computer System with a Multiaccess Network. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Rose , Francine Berman Mapping with External I/O : A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Catherine E. Houstis Allocation of Real-Time Applications to Distributed Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Shau-Ping Lo , Virgil D. Gligor Properties of Multiprocessor Scheduling Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Bilha Mendelson , Gabriel M. Silberman An Improved Mapping of Data Flow Programs on a VLSI Array of Processors. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar , Lalit M. Patnaik An Architecture for CSP and Its Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] R. B. Shu , H. C. Du A Reliable Design of Parallel Processor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Vladimir Cherkassky , Miroslaw Malek Graceful Degradation of Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Qing Yang , Laxmi N. Bhuyan Design and Analysis of a Decentralized Multiple-Bus Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv Gupta , Mary Lou Soffa A Reconfigurable LIW Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrad Yasrebi , James C. Browne , Dharma P. Agrawal Analysis and Design of Parallel Algorithms and Implementations for Some Image Processing Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Dionisios I. Reisis , Viktor K. Prasanna Parallel Image Processing On Enhanced Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Hwang , Dongseung Kim Parallel Pattern ClusterIng on a Multiprocessor with Orthogonally Shared Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Viktor K. Prasanna , Sarma Sastry A General Purpose VLSI Array for Efficient Signal and Image Processsing. [Citation Graph (0, 0)][DBLP ] Conf ] Allen L. Gorin , Allan J. Silberger , Louis Auslander Computing the Two-Dimensional Discrete Fourier Transform on the ASPEN Parallel Computer Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] 