Conferences in DBLP
Jonathan Bertoni , Wen-Hann Wang Multiple Interleaved Bus Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] William Tsun-Yuk Hsu , Pen-Chung Yew The Performance of Hierarchical Systems with Wiring Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Surapong Auwatanamongkol , Prasenjit Biswas A Hybrid Architecture and Adaptive Scheduling for Parallel Execution of Logic Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Kay A. Robbins , Steven Robbins Bus Conflicts for Logical Memory Banks on a Cray Y-MP Type Processor System. [Citation Graph (0, 0)][DBLP ] Conf ] Hong Wang , Qing Yang Prime Cube Graph Approach for Processor Allocation in Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Woei Lin Communication-Efficient Vector Manipulations on Binary N-Cubes. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi Jain , John Werth , James C. Browne A General Model for Scheduling of Parallel Computations and its Application to Parallel I/O Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Hong-Men Su , Pen-Chung Yew Efficient Interprocessor Communication on Distributed Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Konicek , Tracy Tilton , Alexander V. Veidenbaum , Chuan-Qi Zhu , Edward S. Davidson , Ruppert A. Downing , Michael J. Haney , Manish Sharma , Pen-Chung Yew , P. Michael Farmwald , David J. Kuck , Daniel M. Lavery , Robert A. Lindsey , D. Pointer , John T. Andrews , Thomas Beck , T. Murphy , Stephen W. Turner , Nancy J. Warter The Organization of the Cedar System. [Citation Graph (0, 0)][DBLP ] Conf ] Rudolf Eigenmann , Jay Hoeflinger , Greg Jaxon , Zhiyuan Li , David A. Padua Restructuring Fortran Programs for Cedar. [Citation Graph (0, 0)][DBLP ] Conf ] Perry A. Emrath , Mark S. Anderson , Richard R. Barton , Robert E. McGrath The Xylem Operating System. [Citation Graph (0, 0)][DBLP ] Conf ] Kyle Gallivan , William Jalby , Stephen W. Turner , Alexander V. Veidenbaum , Harry A. G. Wijshoff Preliminary Performance Analysis of the Cedar Multiprocessor Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] George E. Daddis Jr. , Hwa C. Torng The Concurrent Execution of Multiple Instruction Streams on Superscalar Processors. [Citation Graph (0, 0)][DBLP ] Conf ] R. Guru Prasadh , Chuan-lin Wu A Benchmark Evaluation of a Multi-threaded RISC Processor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Joy Shetler , Steven E. Butner Multiple Stream Execution on the DART Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Won Woo Park , Donald S. Fussell , Roy M. Jenevein Performance Advantages of Multithreaded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Jiyuan Yang , Lubomir Bic , Alexandru Nicolau A Mapping Strategy for MIMD Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas B. Berg , Shin-Dug Kim , Howard Jay Siegel Impact of Temporal Juxtaposition on the Isolated Phase Optimization Approach to Mapping an Algorithm to Mixed-Mode Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Linda F. Wilson , Mario J. Gonzalez Manipulation of Parallel Algorithms to Improve Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Bilha Mendelson , Israel Koren Using Simulated Annealing for Mapping Algorithms onto Data Driven Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Thang Tran , Chuan-lin Wu Microprocessor Architecture with Multi-Bit Scoreboard Concurrency Control. [Citation Graph (0, 0)][DBLP ] Conf ] Paul T. Hulina , Lee D. Coraor , Shih-Wei Sun Performance Analysis of an Address Generation Coprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur Abnous , Roni Potasman , Nader Bagherzadeh , Alexandru Nicolau A Percolation Based VLIW Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Ray Simar Jr. The TMS32OC4O and it's Application Development Environment: A DSP for Parallel Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Kanad Ghose , Der-Chung Cheng Efficient Synchronization Schemes for Large-Scale Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Matsumoto , Tomoyuki Tanaka , Takao Moriyama , Shigeru Uzuhara MISC: A Mechanism for Integrated Synchronization and Communication Using Snoop Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Hwang , Shisheng Shang Wired-NOR Barrier Synchronization for Designing Large Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Tong Chen , Chuan-Qi Zhu A New Synchronization Mechanism. [Citation Graph (0, 0)][DBLP ] Conf ] Ram Raghavan , John P. Hayes Scalar-Vector Memory Interference in Vector Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Sy-Yen Kuo , Ahmed Louri , Sheng-Chiech Liang Design and Evaluation of Fault-Tolerant Interleaved Memory Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Chandra S. Joshi , Brad A. Reger , John R. Feehrer Memory System for a Statically Scheduled Supercomputer. [Citation Graph (0, 0)][DBLP ] Conf ] Dhabaleswar K. Panda , Kai Hwang Message Vectorization for Converting Multicomputer Programs to Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Shridhar B. Shukla , Dharma P. Agrawal Allocation and Communication in Distributed Memory Multiprocessors for Periodic Real-Time Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Carl J. Beckmann , Constantine D. Polychronopoulos Broadcast Networks for Fast Synchronization. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Fraigniaud , Ching-Tien Ho Arc-Disjoint Spanning Trees on Cube-Connected Cycles Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Luiz André Barroso , Michel Dubois Cache Coherence on a Slotted Ring. [Citation Graph (0, 0)][DBLP ] Conf ] Jesse Zhixi Fang , Mi Lu A Solution of Cache Ping-Pong Problem in RISC Based Parallel Processing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Per Stenström , Fredrik Dahlgren , Lars Lundberg A Lockup-Free Multiprocessor Cache Design. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory T. Byrd , Bruce Delagi Streamline: Cache-Based Message Passing in Scalable Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth E. Batcher Decomposition of Perfect Shuffle Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Chingyuh Jan , A. Yavuz Oruç Fast Self-Routing Permutation Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Nabanita Das , Krishnendu Mukhopadhyaya , Jayasree Dattagupta On Self-Routable Permutations in Benes Network. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyong Liu , Jia-Huai You Realizing Frequently Used Permutations on Syncube. [Citation Graph (0, 0)][DBLP ] Conf ] Jih-Kwon Peir , Kimming So , Ju-Ho Tang Inter-Section Locality of Shared Data in Parallel Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Chin Wang , Michel Dubois , Faye A. Briggs Analytical Modeling for Finite Cache Effects. [Citation Graph (0, 0)][DBLP ] Conf ] Sandra Johnson Baylor , Yarsun Hsu The Effects of Network Delays on the Performance of MIN-Based Cache Coherence Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Kanad Ghose , Sreenivas Simhadri A Cache Coherency Mechanism with Limited Combining Capabilities for MIN-Based Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Manish K. Gupta , David A. Padua Effects of Program Parallelization and Stripmining Transformation on Cache Performance in a Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Yao-Ming Yeh , Tse-Yun Feng Fault Tolerant Routing on a Class of Rearrangeable Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Schwederski , Eduard Bernath , Gerhard Roos , Wayne G. Nation , Howard Jay Siegel Fault Side-Effects in Fault Tolerant Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard L. Menezes , Umesh Bakhru , Randolph Sergent New Bounds on the Reliability of Two Augmented Shuffle-Exchange Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Nian-Feng Tzeng A Reliable Butterfly Network for Distributed-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] C. Jimmy Shih , Kenneth E. Batcher Multiple-Fault Tolerant Cube-Connected Cycles Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Hallo Ahmed , Lars-Erik Thorelli , Johan Wennlund An Enhanced Data-Driven Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Mark R. Thistle A Fine Grain MIMD System with Hybrid Event-Driven/Dataflow Synchronization for Bit-Oriented Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Tzi-cker Chiueh Liger: A Hybrid Dataflow Architeture Exploiting Data/Control Locality. [Citation Graph (0, 0)][DBLP ] Conf ] Adnan K. Shaout , Daniel Smyth Data flow Model for a Hypercube Multiprocessing Network. [Citation Graph (0, 0)][DBLP ] Conf ] Kourosh Gharachorloo , Anoop Gupta , John L. Hennessy Two Techniques to Enhance the Performance of Memory Consistency Models. [Citation Graph (0, 0)][DBLP ] Conf ] Rajendra V. Boppana , C. S. Raghavendra Efficient Storage Schemes for Arbitrary Size Square Matrices in Parallel Processors with Shuffle-Exchange Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner Creutzburg , Lutz Andrews Recent Results on the Parallel Access to Tree-Like Data Structures: The Isotropic Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Shlomo Weiss Multiple-Port Memory Access in Decoupled Architecture Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Susan J. Eggers , Tor E. Jeremiassen Eliminating False Sharing. [Citation Graph (0, 0)][DBLP ] Conf ] T. V. Lakshman , Dipak Ghosal , Yennun Huang , Satish K. Tripathi Effective Load and Resource Sharing in Parallel Protocol-Processing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Moon-Jung Chung , Yunmo Chung A Distributed Token-Driven Technique for Parallel Zero-Delay Logic Simulation on Massively Parallel Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Alireza Kavianpour , Nader Bagherzadeh Parallel Hough Transform for Image Processing on a Pyramid Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] H. W. Park , T. Alexander , K. S. Eo , Y. Kim UWGSP4: Merging Parallel and Pipelined Architectures for Imaging and Graphics. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Jin , Simin H. Pakzad , Ali R. Hurson Application of Neural Networks in Handling Large Incomplete Databases: VLSI Design and Performance Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed El-Amawy Branch-and-Combine Clocking of Arbitrarily Large Computing Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Michael A. Palis , Sanguthevar Rajasekaran , David S. L. Wei Emulation of a PRAM on Leveled Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Minze V. Chien , A. Yavuz Oruç Optimal Non blocking Networks with Pin Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Shuichi Sakai , Yuetsu Kodama , Yoshinori Yamaguchi Design and Implementation of a Versatile Interconnection Network in the EM-4. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Tsuen Chen , Chia-Cheng Liu , Ming-Yi Fang A Massively Parallel Processing Unit with a Reconfigurable Bus System RIPU. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaola Lin , Philip K. McKinley , Lionel M. Ni Performance Evaluation of Multicast Wormhole Routing in 2D-Mesh Multicomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Ted H. Szymanski O (log N / log log N) Randomized Routing in Degree-log N "Hypermeshes". [Citation Graph (0, 0)][DBLP ] Conf ] Ted H. Szymanski , Chien Fang Randomized Routing of Virtual Connections in Extended Banyans. [Citation Graph (0, 0)][DBLP ] Conf ] Mohan Kumar , Lalit M. Patnaik Fault-Tolerant Message Routing and Error Detection Schemes for the Extended Hypercube. [Citation Graph (0, 0)][DBLP ] Conf ] Kia Makki , Paul Banta , Ken Been , Roy Ogawa Two Algorithms for Mutual Exclusion in a Distributed System. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Shyen E. Chen , Young Man Kim , Ming T. Liu A Modular High-Speed Switching Network for Integration of Heterogeneous Computing Resources. [Citation Graph (0, 0)][DBLP ] Conf ] Lan Jin , Lan Yang , Chane L. Fullmer , Brian Olson Dynamically Reconfigurable Architecture of a Transputer-Based Multicomputer System. [Citation Graph (0, 0)][DBLP ] Conf ] Kien A. Hua , Chiang Lee , Honesty C. Young A Cell-Based Data Partitioning Strategy for Efficient Load Balancing in A Distributed Memory Multicomputer Database System. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Ogbonna Esonu , Asim J. Al-Khalili , Salim Hariri Area Efficient Computing Structures for Concurrent Error Detection in Systolic Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] M. Sultan Alam , Rami G. Melhem Channel Multiplexing in Modular Fault Tolerant Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Mazin S. Algudady , Chita R. Das , Matthew Thazhuthaveetil A Cache-Based Checkpointing Scheme for MIN-Based Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Balasubramanian , Prithviraj Banerjee CRAFT: Compiler-Assisted Algorithm-Based Fault Tolerance in Distributed Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Bob Janssens , W. Kent Fuchs Experimental Evaluation of Multiprocessor Cache-Based Error Recovery. [Citation Graph (0, 0)][DBLP ] Conf ] Noboru Tanabe , Takashi Suzuoka , Sadao Nakamura , Yasushi Kawakura , Shigeru Oyanagi Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGY. [Citation Graph (0, 0)][DBLP ] Conf ] Hsing-Lung Chen , Nian-Feng Tzeng Fault-Tolerant Resource Placement in Hypercube Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Shahid H. Bokhari Multiphase Complete Exchange on a Circuit Switched Hypercube. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Hsiang Chou , David Hung-Chang Du Hierarchical Uni-Directional Hypercubes. [Citation Graph (0, 0)][DBLP ] Conf ] Yann-Hang Lee , Sandra E. Cheung , Jih-Kwon Peir Consecutive Requests Traffic Model in Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Nian-Feng Tzeng An Approach to the Performance Improvement of Multistage Interconnection Networks with Nonuniform Traffic Spots. [Citation Graph (0, 0)][DBLP ] Conf ] Eugene Pinsky , Paul A. Stirpe Modeling and Analysis of "Hot Spots" in an Asynchronous NxN Crossbar Switch. [Citation Graph (0, 0)][DBLP ] Conf ] Byung-Chang Kang , Gyungho Lee , Richard Y. Kain Performance of Multistage Combining Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Lizy Kurian John , Matthew Thazhuthaveetil Effect of Hot Spots on Multiprocessor Systems Using Circuit Switched Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Rami G. Melhem , John C. Ramirez Reconfiguration of Computational Arrays with Multiple Redundancy. [Citation Graph (0, 0)][DBLP ] Conf ] Yoon-Hwa Choi Reconfigurable Multipipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Pei-Ji Yang , Sing-Ban Tien , C. S. Raghavendra Embedding of Multidimensional Meshes on to Faulty Hypercubes. [Citation Graph (0, 0)][DBLP ] Conf ] Jean Frédéric Myoupo A Way of Deriving Linear Systolic Arrays from a Mathematical Algorithm Description: Case of the Warshall-Floyd Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Hughey , Daniel P. Lopresti B-SYS: A 470-Processor Programmable Systolic Array. [Citation Graph (0, 0)][DBLP ] Conf ] Mahib Rahman , David G. Meyer General Analytic Models for the Performance Analysis of Unique and Redundant Path Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jianxun Ding , Laxmi N. Bhuyan Performance Evaluation of Multistage Interconnection Networks with Finite Buffers. [Citation Graph (0, 0)][DBLP ] Conf ] Qing Yang Effects of Arbitration Protocols on the Performance of Multiple-Bus Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Jiun-Ming Hsu , Prithviraj Banerjee Performance Evaluation of Hardware Support for Message Passing in Distributed Memory Multicomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Guo-Jie Li , Benjamin W. Wah Parallel Iterative Refining A* Search. [Citation Graph (0, 0)][DBLP ] Conf ] Sivarama P. Dandamudi , James C. Y. Chow Scheduling in Parallel Database Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Bhagirath Narahari , Hyeong-Ah Choi Allocating Partitions to Task Precedence Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Hyeong-Ah Choi , Bhagirath Narahari Algorithms for Mapping and Partitioning Chain Structured Parallel Computations. [Citation Graph (0, 0)][DBLP ] Conf ] Dipak Ghosal , Amar Mukherjee , Ramakrishna Thurimella , Yaacov Yesha Mapping Task Trees onto a Linear Array. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Horie , Hiroaki Ishihata , Toshiyuki Shimizu , Sadayuki Kato , Satoshi Inano , Morio Ikesaka AP1000 Architecture and Performance of LU Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos G. Bourbakis , Fotios Barlos Performance Modeling of Quartet Multiprocessor Kernels with Failures. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan R. Agre , Peter A. Tinker An Architecture for the Rollback Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Marek Tudruj , Miroslav Thor The Architecture of a Multilayer Dynamically Reconfigurable Transputer System. [Citation Graph (0, 0)][DBLP ] Conf ] Tsau Young Lin Concurrent Automata and Parallel Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid R. Arabnia Towards a General-Purpose Parallel System for Imaging Operations. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Chen , Li Zhu A Fast 1024-Point FFT Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Kuang Chou , David Y. Y. Yun A Parallel Architecture for Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay R. Deshpande , Prem P. Jain Improving the Efficiency of Multi-rate Signal Processing Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Jai-Hoon Chung , Hyunsoo Yoon , Seung Ryoul Maeng A Systolic Array Exploiting the Inherent Parallelisms of Artificial Neural Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Gang Che , Yan-Da Li , Yue Jiao A Fault-Tolerant Design of CFM VLSI Parallel Array for Yield enhancement and Reliability Improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Gerhard Raupp , Harald H. Richter The MULTITOP Parallel Computers for ASDEX-Upgrade. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald F. DeMara , Dan I. Moldovan Performance Indices for Parallel Marker-Propagation. [Citation Graph (0, 0)][DBLP ] Conf ] Walter H. Burkhardt Performance Penalty by Communication in Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph E. Hoag , Eugene D. Brooks III Simulation Results for a Scalable Coherent Cache System with Incomplete Directory State. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiwei Xu A Hardware Synchronization Technique for Structured Parallel Computing. [Citation Graph (0, 0)][DBLP ] Conf ] David W. Opitz A Study of Single Bit Spin Waiting Alternatives. [Citation Graph (0, 0)][DBLP ] Conf ] Chang Nian Zhang , H. D. Cheng Mapping Multiple Problem Instances into a Single Systolic Array with Application to Concurrent Error Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Jung Hwan Kim , Phill K. Rhee A Parallel Reconfiguration Algorithm for WSI/VLSI Processor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Roni Hardon , Shlomit S. Pinter Choosing the Right Grains for Data Flow Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Franz Schreiner , Gerhard Zimmermann Efficient Production System Execution on the PESA Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey S. Clary , Suraj C. Kothari Implementation of the Hopfield Neural Network on the MasPar System. [Citation Graph (0, 0)][DBLP ] Conf ] Guohua Jin , Xuejun Yang , Fujie Chen Loop Staggering Loop Staggering and Compacting: Restructuring Techniques for Thrashing Problem. [Citation Graph (0, 0)][DBLP ] Conf ] K. Gopinath Memory Models Compiler Optimizations and P-RISC. [Citation Graph (0, 0)][DBLP ] Conf ] Sourav Bhattacharya , Chungti Liang , Wei-Tek Tsai Inverted Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Abdou Youssef Cartesian Product Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Vipin Chaudhary , Bikash Sabata , Jake K. Aggarwal The VEDIC Network for Multicomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Yi Pan , Y. H. Chuang Block Shift Network: A New Interconnection-Network for Efficient Parallel Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Donald B. Bennett , Stephen M. Sohn Layered Networks A New Class of Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jehoshua Bruck , Robert Cypher , Ching-Tien Ho On the Construction of Fault-Tolerant Cube-Connected Cycles Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas M. Blough , Wei-Kang Tsai Binary Hypermesh Networks for Parallel Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Kang Tsai , Nader Bagherzadeh , Young C. Kim Hypermesh: A Combined Quad Tree and Mesh Network for Parallel Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi N. Sibai , Abdullah A. Abonamah C2SC: A Four-Path Fault Tolerant Interconnection Network. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Padmanabhan On Multistage Networks with Ternary Switching Elements. [Citation Graph (0, 0)][DBLP ] Conf ] Guoning Liao , Joar Østby , Oddvar Søråsen , Yngvar Lundh Self Synchronizing Data Transfer Schemes for Multicomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Barry G. Douglass A Parallel Computer Architecture Based on Optical Shuffle Interprocessor Connections. [Citation Graph (0, 0)][DBLP ] Conf ] A. Yavuz Oruç , Vinod G. J. Peris , M. Yaman Oruç Parallel Modular Arithmetic on a Permutation Network. [Citation Graph (0, 0)][DBLP ] Conf ] Chunming Qiao , Rami G. Melhem , Donald M. Chiarulli , Steven P. Levitan Multicasting in Optical Bus Connected Processors Using Coincident Pulse Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Robert A. Rowley , Bella Bose Fault-Tolerant Ring Embedding in de Bruijn Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Swie-Tsing Tan , David Hung-Chang Du On Embedding Virtual Incomplete Hypercubes into WDM-Based High-Speed Optical Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Yi Fang , Wen-Tsuen Chen Embedding Large Binary Trees to Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Sing-Ban Tien , C. S. Raghavendra Simulation of SIMD Algorithms on Faulty Hypercubes. [Citation Graph (0, 0)][DBLP ] Conf ] Hideharu Amano , Kalidou Gaye A Batcher Double Omega Network with Combining. [Citation Graph (0, 0)][DBLP ] Conf ] Shymal Chawdhusy , Mark A. Holliday Stability and Performance of Alternative Two-level Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Jing Hsu Fibonacci Cubes: Properties of an Asymmetric Interconnection Topology. [Citation Graph (0, 0)][DBLP ] Conf ] 