Conferences in DBLP
Nian-Feng Tzeng Design of a Novel Combining Structure for Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel M. Dias , Manoj Kumar Preventing Congestion in Multistage Networks in the Presence of Hotspots. [Citation Graph (0, 0)][DBLP ] Conf ] Wing S. Ho , Derek L. Eager A Novel Strategy for Controlling Hot Spot Congestion. [Citation Graph (0, 0)][DBLP ] Conf ] Lance Kurisaki , Tomás Lang Multistage Networks Including Traffic with Real-Time Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Sang Lyul Min , Jean-Loup Baer A Timestamp-based Cache Coherence Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Craig B. Stunkel , W. Kent Fuchs Analysis of Hypercube Cache Performance Using Address Traces Generated by TRAPEDS. [Citation Graph (0, 0)][DBLP ] Conf ] Haim E. Mizrahi , Jean-Loup Baer , Edward D. Lazowska , John Zahorjan Extending the Memory Hierarchy into Multiprocessor Interconnection Networks: A Performance Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Laxmi N. Bhuyan , Bao-Chyn Liu , Irshad Ahmed Analysis of MIN Based Multiprocessors with Private Cache Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Edward C. Bronson , Thomas L. Casavant , Leah H. Jamieson Experimental Application-Driven Architecture Analysis of an SIMD/MIMD Parallel Processing System. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Kumar , Kimming So Trace Driven Simulation for Studying MIMD Parallel Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Laxmi N. Bhuyan , Hong Jiang , Dipak Ghosal From Interconnection Network To Task Level Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Sandra Johnson Baylor , Bharat Deep Rathi A Study of the Memory Reference Behavior of Engineering/Scientific Applications in Parallel Processors. [Citation Graph (0, 0)][DBLP ] Conf ] M. Seetha Lakshmi , Philip S. Yu Analysis of Parallel Processing Architectures for Database Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Myoung-Ho Kim , Sakti Pramanik On the Data Distribution Problems for Range Queries. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenqiang Fan , Kam-Hoi Cheng A Simultaneous Access Priority Queue. [Citation Graph (0, 0)][DBLP ] Conf ] Constantinos T. Davarakis , Dimitris G. Maritsas A Parallel Associative Query Set of Algorithms (PASQ-set) and the MULTI-layer Associative Processor Model. [Citation Graph (0, 0)][DBLP ] Conf ] Ted H. Szymanski On the Permutation Capability of a Circuit-Switched Hypercube. [Citation Graph (0, 0)][DBLP ] Conf ] Philip J. Bernhard , Harry B. Hunt III , Daniel J. Rosenkrantz Compaction of Message Patterns into Space-Efficient Representations for Multiprocessor Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Seth Abraham , Krishnan Padmanabhan An Analysis of the Twisted Cube Topology. [Citation Graph (0, 0)][DBLP ] Conf ] Oscar H. Ibarra , Stephen M. Sohn On Mapping Systolic Algorithms onto the Hypercube. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Li , Richard Schaefer A Hypercube Shared Virtual Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Bisiani , Andreas Nowatzyk , Mosur Ravishankar Coherent Shared Memory on a Distributed Memory Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Larry D. Wittie , Creve Maples MERLIN: Massively Parallel Heterogeneous Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Lothar Borrmann , Martin Herdieckerhoff Parallel Processing Performance in a Linda System. [Citation Graph (0, 0)][DBLP ] Conf ] Kun-Lung Wu , W. Kent Fuchs , Janak H. Patel Cache-Based Error Recovery for Shared Memory Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip F. Chimento Jr. , Kishor S. Trivedi Completion Times of Programs on Concurrent Processors with Failure and Repair. [Citation Graph (0, 0)][DBLP ] Conf ] Tsang-Ling Sheu , Woei Lin , Chita R. Das , Mary Jane Irwin Distributed Fault Diagnosis in the Butterfly Parallel Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Arif Ghafoor , Sohail Sheikh , Patrick Solé Distance-Transitive Graphs for Fault-Tolerant Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Shahram Latifi , Ahmed El-Amawy On Folded Hypercubes. [Citation Graph (0, 0)][DBLP ] Conf ] Piotr Berman , Juan A. Garay Efficient Agreement on Bounded-Degree Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Chungti Liang , Yigang Chen , Wei-Tek Tsai Embedding of Linear Array and Binary Tree in Cubical Ring Connected Cycles Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory T. Byrd , Nakul P. Saraiya , Bruce Delagi Multicast Communication in Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] A. P. Wim Böhm , John R. Gurd , Yong Meng Teo The Effect of Iterative Instructions in Dataflow Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Keshab K. Parhi , David G. Messerschmitt Fully-Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding. [Citation Graph (0, 0)][DBLP ] Conf ] Tetsuya Higuchi , Tatsumi Furuya , Hiroyuki Kusumoto , Ken'ichi Handa , Akio Kokubu The Prototype of a Semantic Network Machine IXM. [Citation Graph (0, 0)][DBLP ] Conf ] Badie A. Taha , Hilda M. Standley A General Model for Memory Interference in a Multiprocessor System with Memory Hierarchy. [Citation Graph (0, 0)][DBLP ] Conf ] Sandra Johnson Baylor , Faye A. Briggs The Effects of Cache Coherence on the Performance of Parallel PDE Algorithms in Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] David T. Harper III Address Transformations to Increase Memory Performance. [Citation Graph (0, 0)][DBLP ] Conf ] B. Ramakrishna Rau , Michael S. Schlansker , David W. L. Yen The Cydram 5 Stride-Insensitive Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] Suresh C. Kothari , Heekuck Oh , Ethan Gannet Optimal Designs of Linear Flow Systolic Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Zhijun Tong The Optimal Assignment of Sequential Programs to a Pipelined Linear Processor Array. [Citation Graph (0, 0)][DBLP ] Conf ] Hee Yong Youn , Adit D. Singh A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Jorge L. Aravena , Ahmed El-Amawy Time Optimal Operation of Heterogeneous Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Hsing-Lung Chen , Nian-Feng Tzeng Enhanced Incomplete Hypercubes. [Citation Graph (0, 0)][DBLP ] Conf ] David Nassimi A Fault-Tolerant Routing Algorithm for BPC Permutations on Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Koppelman , A. Yavuz Oruç A Self-Routing Permutation Network. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Schwederski , Howard Jay Siegel , Thomas L. Casavant Task Migration Transfers in Multistage Cube Based Parallel Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Carla Schlatter Ellis , David Kotz Prefetching in File Systems for MIMD Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] A. L. Narasimha Reddy , Prithviraj Banerjee Performance Evaluation of Multiple-Disk I/O Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Kadota , Katsuyuki Kaneko , Yuji Tanikawa , Tatsuo Nogi VLSI Parallel Computer with Data Transfer Network: ADENA. [Citation Graph (0, 0)][DBLP ] Conf ] Abhaya Asthana , H. V. Jagadish , Boyd Mathews Impact of Advanced VLSI Packaging on the Design of a Large Parallel Computer. [Citation Graph (0, 0)][DBLP ] Conf ] 