Conferences in DBLP
Toshihiro Hanawa , Hideharu Amano , Yoshifumi Fujikawa Multistage Interconnection Networks with Multiple Outlets. [Citation Graph (0, 0)][DBLP ] Conf ] Young-Keun Park , Gyungho Lee A High Throughput Packet-Switching Network with Neural Network Controlled Bypass Queueing and Multiplexing. [Citation Graph (0, 0)][DBLP ] Conf ] Prasant Mohapatra , Sheldon Wong , Chita R. Das Performance Analysis of Combining Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Seung-Woo Seo , Tse-Yun Feng A General Inside-Out Routing Algorithm for a Class of Rearrangeable Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Jurczyk , Thomas Schwederski , R. Born , Howard Jay Siegel , Seth Abraham Strategies for the Massively Parallel Simulation of Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Laxmi N. Bhuyan , Ashwini K. Nanda , Tahsin Askar Performance and Reliability of the Multistage Bus Network. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed El-Amawy , Priyalal Kulasinghe Theory of Generalized Branch and Combine Clock Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew C. Flavell , Yoshizo Takahashi Continuum: A Hybrid Time/Space Communications Paradigm for K -ary N -cubes. [Citation Graph (0, 0)][DBLP ] Conf ] Jen-peng Huang , S. Lakshmivarahan , Sudarshan K. Dhall Analysis of Interconnection Networks Based on Cayley Graphs of Strong Generating Sets. [Citation Graph (0, 0)][DBLP ] Conf ] Subburajan Ponnuswamy , Vipin Chaudhary A Comparative Study of Star Graphs and Rotator Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald Fernandes , Donald K. Friesen , Arkady Kanevsky Efficient Routing and Broadcasting in Recursive Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Thomas Breznay , Mario Alberto López A Class of Static and Dynamic Hierarchical Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Debashis Basak , Dhabaleswar K. Panda Designing Large Hierarchical Multiprocessor Systems under Processor, Interconnection, and Packaging Advancements. [Citation Graph (0, 0)][DBLP ] Conf ] V. Carl Hamacher , Hong Jiang Comparison of Mesh and Hierarchical Networks for Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Kemal Efe , Antonio Fernández Computational Properties of Mesh Connected Trees: Versatile Architectures for Parallel Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Kogge EXECUBE - A New Architecture for Scalable MPPs. [Citation Graph (0, 0)][DBLP ] Conf ] Richard P. Halverson Jr. , Art Lew Programming with Functional Memory. [Citation Graph (0, 0)][DBLP ] Conf ] William E. Cohen , Henry G. Dietz , J. B. Sponaugle Dynamic Barrier Architecture for Multi-Mode Fine Grain Parallelism Using Conventional Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Hsiao-chen Chung , Chuan-lin Wu , James Rakes , Peter J. Zievers , Yin-Kuan Lin Design and Evaluation of a Multiprocessor Architecture with Decentralized Control. [Citation Graph (0, 0)][DBLP ] Conf ] Fotios K. Liotopoulos , Suresh Chalasani Nonblocking Operation of Asymmetrical Clos Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Tse-Yun Feng , Yanggon Kim A New Tag Scheme and Its Tree Representation for a Shuffle-Exchange Network. [Citation Graph (0, 0)][DBLP ] Conf ] B. Park , K. Watson On the Rearrangeability of Reverse Shuffle/Exchange Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Masashi Sasahara , Jun Terada , Luo Zhou , Kalidou Gaye , Jun-ichi Yamato , Satoshi Ogura , Hideharu Amano SNAIL: A Multiprocessor Based on the Simple Serial Synchronized Multistage Interconnection Network Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] De-Lei Lee , Kenneth E. Batcher On Sorting Multiple Bitonic Sequences. [Citation Graph (0, 0)][DBLP ] Conf ] Bing-rung Tsai , Kang G. Shin Sequencing of Concurrent Communication Traffic in a Mesh Multicomputer with Virtual Channels. [Citation Graph (0, 0)][DBLP ] Conf ] David F. Robinson , Philip K. McKinley , Betty H. C. Cheng Optimal Multicast Communication in a Wormhole-Routed Torus Networks. [Citation Graph (0, 0)][DBLP ] Conf ] José Duato A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Yeimkuan Chang , Laxmi N. Bhuyan , Akhilesh Kumar A Distributed Cache Coherence Protocol for Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Fong Pong , Per Stenström , Michel Dubois An Integrated Methodology for the Verification of Directory-Based Cache Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Fredrik Dahlgren , Per Stenström Reducing the Write Traffic for a Hybrid Cache Protocol. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaodong Zhang , Yong Yan Latency Analysis of CC-NUMA and CC-COMA Rings. [Citation Graph (0, 0)][DBLP ] Conf ] Santosh Pande , Kleanthis Psarris Compiling Functional Parallelism on a Family of Different Distributed Memory Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Sesh Venugopal , Vijay K. Naik Deadlock Free Asynchronous Communication Strategies for Unstructured Computations on iPSC/860. [Citation Graph (0, 0)][DBLP ] Conf ] Vipul Gupta , Eugen Schenfeld A Comparative Performance Study of an Interconnection Cached Network. [Citation Graph (0, 0)][DBLP ] Conf ] Kanad Ghose , R. Kym Horsell , Nitin K. Singhvi Hybrid Multiprocessing in OPTIMUL : A Multiprocessor for Distributed and Shared Memory Multiprocessing with WDM Optical Fiber Interconnections. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Agarwala , Chita R. Das A Shared Memory Environment for Hypercubes. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin Gamsa , Orran Krieger , Michael Stumm Optimizing IPC Performance for Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Lizy Kurian John , Bermjae Choi , Paul T. Hulina , Lee D. Coraor Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Jae Young Lee , Hee Yong Youn PSIM: Periodically Shifted Interleaved Memory System. [Citation Graph (0, 0)][DBLP ] Conf ] N. Ranganathan , Satish Venugopal An Efficient VLSI Architecture for Template Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth N. Ellis , Winser E. Alexander Block Data Processing Using Commercial Processors. [Citation Graph (0, 0)][DBLP ] Conf ] José Salinas , Fabrizio Lombardi Rank Order Filtering on an Array With Faulty Processors. [Citation Graph (0, 0)][DBLP ] Conf ] James B. Armstrong , Mark A. Nichols , Howard Jay Siegel , Kenneth H. Casey Image Correlation: A Case Study to Examine SIMD/MIMD Trade-offs for Scalable Parallel Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Chouki Aktouf , Chantal Robach , Guy Mazaré Fault-Tolerant Routing Algorithms for a Massively Parallel Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Qing Yang , Sridhar Adina A One's Complement Cache Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Ricardo Bianchini , Thomas J. LeBlanc Can High Bandwidth and Latency Justify Large Cache Blocks in Scalable Multiprocessors? [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Hung Chi Compiler Optimization Technique for Data Cache Prefetching Using a Small CAM Array. [Citation Graph (0, 0)][DBLP ] Conf ] Randall L. Hyde , Brett D. Fleisch Degenerate Sharing. [Citation Graph (0, 0)][DBLP ] Conf ] Jeng-Ping Lin , Shih-Chang Wang , Sy-Yen Kuo Error Recovery in Parallel Systems of Pipelined Processors with Caches. [Citation Graph (0, 0)][DBLP ] Conf ] K. Gopinath , M. K. Krishna Narasimhan , B. H. Lim , A. Agarwal Performance of Switch Blocking on Multithreaded Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Shyh-Kwei Chen , W. Kent Fuchs , Wen-mei W. Hwu An Analytical Approach to Scheduling Code for Superscalar and VLIW Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Wallace , Nader Bagherzadeh Performance Issues of a Superscalar Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Capitanio , Nikil D. Dutt , Alexandru Nicolau Partitioning of Variables for Multiple-Register-File VLIW Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] 