Conferences in DBLP
Albert G. Greenberg , Udi Manber A Probabilistic Pipeline Algorithm for K-Selection on the Tree Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Edward W. Felten , Steve W. Otto , Scott Karlin The Traveling Salesman Problem on a Hypercubic, MIMD Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Larry Rudolph , William L. Steiger Subset Selection in Parallel. [Citation Graph (0, 0)][DBLP ] Conf ] Richard C. Paige , Clyde P. Kruskal Parallel Algorithms for Shortest Path Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Eugene D. Brooks III Performance of the Butterfly Processor-Memory Interconnection in a Vector Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel A. Reed , Merrell L. Patrick Iterative Solution of Large, Sparse, Linear Systems on a Static Data Flow Architecture: Performance Studies. [Citation Graph (0, 0)][DBLP ] Conf ] Wilfried Oed , Otto Lange On the Effective Bandwidth of Interleaved Memories in Vector Processor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Abhiram G. Ranade Interconnection Networks And Parallel Memory Organizations For Array Processing. [Citation Graph (0, 0)][DBLP ] Conf ] H. Barad , Dan I. Moldovan A Systems Approach to Mapping a Karhunen-Loeve Transform into a Systolic Array. [Citation Graph (0, 0)][DBLP ] Conf ] Manoel Fernando Tenorio , Dan I. Moldovan Mapping Production Systems into Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Lionel M. Ni , Ching-Farn Eric Wu Design Trade-offs for Process Scheduling in Tightly Coupled Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] John C. Peterson , Jesus O. Tuazon , Don Lieberman , Moshe Pniel The Mark III Hypercube-Ensemble Concurrent Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Mary Diane Palmer Leland On the Power of the Augmented Data Manipulator Network. [Citation Graph (0, 0)][DBLP ] Conf ] Renben Shu , Peter C. Patton BCA : A Bus Connected Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Arndt Bode , Gerhard Fritsch , Wolfgang Händler , Wolfgang Henning , Fridolin Hofmann , Jens Volkert Multi-Grid oriented Computer Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Mark A. Shell , Donald W. Bouldin , Paul D. Manhardt Design and Implementation of a VLSI Systolic Array for Solving Nonlinear Partial Differential Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Allan L. Fisher Memory and Modularity in Systolic Array Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Hwang , Zhiwei Xu Remps: A Reconfigurable Multiprocessor for Scientific Supercomputing. [Citation Graph (0, 0)][DBLP ] Conf ] Amos Fiat , Adi Shamir , Ehud Y. Shapiro Polymorphic Arrays: An Architecture for a Programmable Systolic Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Ehud Y. Shapiro , Shmuel Safra Fast Multiway Merge Using Destructive Operation. [Citation Graph (0, 0)][DBLP ] Conf ] Guo-Jie Li , Benjamin W. Wah MANIP-2 : A Multicomputer Architecture for Evaluating Logic Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Jim A. Crammond A Comparative Study of Unification Algorithms For Or-Parallel Execution of Logic Languages. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmed K. Ezzat , Rakesh Agrawal Making Oneself Known in a Distributed World. [Citation Graph (0, 0)][DBLP ] Conf ] Heinz Mühlenbein , S. Warhaut Concurrent Mulitgrid Methods in an Object-Oriented Environment: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Steven P. Levitan Evaluation Criteria for Communication Structures in Parallel Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Ariel J. Frank , Larry D. Wittie , Arthur J. Bernstein Maintaining Weakly-Consistent Replicated Data on Dynamic Groups of Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi R. Zargham , Ralph D. Purcell A Protocol for Load Balancing on CSMA Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Marsha J. Berger , Shahid H. Bokhari A Partitioning Strategy for PDEs Across Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Mark A. Yoder , Leah H. Jamieson Simulation of a Word Recognition System on Two Parallel Arcitectures. [Citation Graph (0, 0)][DBLP ] Conf ] Clyde P. Kruskal , Larry Rudolph , Marc Snir The Power of Parallel Prefix. [Citation Graph (0, 0)][DBLP ] Conf ] Shaunak Pawagi , I. V. Ramakrishnan Parallel Updates of Graph Properties in Logarithmic Time. [Citation Graph (0, 0)][DBLP ] Conf ] Ten-Hwang Lai , Alan P. Sprague Performance of Parallel Branch-and-Bound Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] David Lefkovitz , Roger Y. Lee , Philip R. Nelson An Embedded Software Design Simulator for ADA Multitasking. [Citation Graph (0, 0)][DBLP ] Conf ] Alan M. Schwartz , Michael C. Loui Dictionary Machines on Cube-Class Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce P. Lester Analysis of Firing Rates in Petri Nets Using Linear Algebra. [Citation Graph (0, 0)][DBLP ] Conf ] Sang Hyun Han Exploitation of Parallelism in Array Loopback Test. [Citation Graph (0, 0)][DBLP ] Conf ] James T. Kuehn , Howard Jay Siegel Extensions to the C Programming Language for SIMD/MIMD Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Fraboul , Nourredine Hifdi Expressing and Exploiting Parallelism on an Experimental MIMD System. [Citation Graph (0, 0)][DBLP ] Conf ] Mark R. Headington , Arthur E. Oldehoeft Open Predicate Path Expressions and their Implementation in Highly Parallel Computing Environments. [Citation Graph (0, 0)][DBLP ] Conf ] Hungwen Li , Ching-Chy Wang , Mark A. Lavin Structured Process: A New Language Attribute for Better Interaction of Parallel Architecture and Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] David Gelernter , Nicholas Carriero , Sarat Chandran , Silva Chang Parallel Programming in Linda. [Citation Graph (0, 0)][DBLP ] Conf ] Mary E. Mace , Robert A. Wagner Globally Optimum Selection of Memory Storage Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Bruce M. Bigler , Stephen J. Allan , R. R. Oldehoeft Parallel Dynamic Storage Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Jean Marc Frailong , William Jalby , Jacques Lenfant XOR-Schemes: A Flexible Data Organization in Parallel Memories. [Citation Graph (0, 0)][DBLP ] Conf ] David Barkai , K. J. M. Moriarty , Claudio Rebbi A Modified Conjugate Gradient Solver for Very Large Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi Mehrotra , Edward F. Gehringer Superlinear Speedup Through Randomized Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Livny , Udi Manber Shift Arithmetic on a Token Ring Network. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Cardelino , Pin-Yee Chen A New Parallel Algorithm for Solving a Complex Function F(Z)=0. [Citation Graph (0, 0)][DBLP ] Conf ] Jack S. Walicki , M. Andrews Parallel Implementation of the LMS Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Tau A. Lea A Load-Sharing Banyan Network. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Kumagai , Kazuo Ikegaya The Two-Dimensional Inverse Omega Network. [Citation Graph (0, 0)][DBLP ] Conf ] Anujan Varma , C. S. Raghavendra Realization of Permutations on Generalized Indra Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Tse-Yun Feng , Wei Young An O(log2 N) Control Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] K. Culick Towards a Theory of Control-Flow and Data-Flow Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Yang-Chang Hong , Thomas H. Payne , Le Baron O. Ferguson An Architecture for a Dataflow Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Sharilyn A. Thoreson , Arlen N. Long A Feasibility Study of a Memory Hierarchy in a Data Flow Environment. [Citation Graph (0, 0)][DBLP ] Conf ] A. Yavuz Oruç , M. Yaman Oruç On Testing Permutation Network Isomorphisms. [Citation Graph (0, 0)][DBLP ] Conf ] Heonshik Shin , Miroslaw Malek Parallel Garbage Collection with Associative Tag. [Citation Graph (0, 0)][DBLP ] Conf ] I. V. Ramakrishnan , Peter J. Varman An Optimal Family of Matrix Multiplication Algorithms on Linear Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] A. J. Field , M. D. Cripps Self-Clocking Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander A. Sawchuk , Bob K. Jenkins , C. S. Raghavendra , Anujan Varma Optical Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Charles E. Leiserson Fat-Trees: Universal Networks for Hardware-Efficient Supercomputing. [Citation Graph (0, 0)][DBLP ] Conf ] Nathaniel J. Davis IV , William Tsun-Yuk Hsu , Howard Jay Siegel Fault Location in Distributed Control Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Mikhail J. Atallah , Michael T. Goodrich Efficient Parallel Solutions to Geometric Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter R. Cappello A Mesh Automaton for Solving Dense Linear Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Hoshino , Takeshi Kamimura , Toshihiro Iida , Tomonori Shirakawa Parallelized ADI Scheme Using GECR (Gauss-Elimination-Cyclic-Reduction) Method and Implementation of Navier-Stokes Equation in the PAX computer. [Citation Graph (0, 0)][DBLP ] Conf ] Guo-Jie Li , Benjamin W. Wah Systolic Processing for Dynamic Programming Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Henry G. Dietz , David Klappholz Refined C: A Sequential Language for Parallel Programming. [Citation Graph (0, 0)][DBLP ] Conf ] Ron Cytron Useful Parallelism in a Multiprocessing Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Nian-Feng Tzeng , Pen-Chung Yew , Chuan-Qi Zhu The Performance of a Fault-Tolerant Multistage Interconnection Network. [Citation Graph (0, 0)][DBLP ] Conf ] Tan Hsiao-Nan RSESS Interconnection Network. [Citation Graph (0, 0)][DBLP ] Conf ] Anujan Varma , C. S. Raghavendra Performance Analysis of a Redundant-Path Interconnection Network. [Citation Graph (0, 0)][DBLP ] Conf ] Haim E. Mizrahi , Israel Koren Evaluating the Cost-Effectiveness of Switches in Processor Array Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence Snyder An Inquiry into the Benefits of Multigauge Parallel Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Robert M. Lougheed , David L. McCubbrey Multi-Processor Architectures For Machine Vision and Image Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard L. Menezes , Roy M. Jenevein KYKLOS : A Linear Growth Fault-Tolerant Interconnection Network. [Citation Graph (0, 0)][DBLP ] Conf ] V. Ashok , Neelam Soundararajan , Roger L. Costello : Distributed Discrete Event Simulation using Dataflow. [Citation Graph (0, 0)][DBLP ] Conf ] Michael L. Campbell Static Allocation for a Data Flow Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] E. Levin Suitability of a Data Flow Architecture for Problems Involving Simple Operations on Large Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Trevor N. Mudge , Humoud B. Al-Sadoun A Semi-Markov Model for the Performance of Multiple-Bus Systems. [Citation Graph (0, 0)][DBLP ] Conf ] William R. Crowther , J. Goodhue , E. Starr , R. Thomas , W. Milliken , T. Blackadar Performance Measurements on a 128-Node Butterfly Parallel Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Elizabeth Williams , Frank Bobrowicz Speedup Predictions on Large Scientific Parallel Programs on Cray X MP Like Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Shimon Edelman , Ehud Y. Shapiro Quadtrees in Concurrent PROLOG. [Citation Graph (0, 0)][DBLP ] Conf ] Hisao Tamaki A Distributed Unification Scheme for Systolic Logic Programs. [Citation Graph (0, 0)][DBLP ] Conf ] G. Jack Lipovski , Manuel V. Hermenegildo B-Log: A Branch and Bound Methodology for the Parallel Execution of Logic Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Toru Ishida , Salvatore J. Stolfo Towards the Parallel Execution of Rules in Production System Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Randy H. Steinvorth , G. F. Taylor , Jack F. McDonald , T. Hunter An Architecture for a Video Rate Fuzzy Golay Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Nobuhiko Koike , Kenji Ohmori MAN-YO : A Special Purpose Parallel Machine for Logic Design Automation. [Citation Graph (0, 0)][DBLP ] Conf ] Chita R. Das , Laxmi N. Bhuyan Reliability Simulation of Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Martin T. Hagan , Howard B. Demuth , Paul Hartono Singgih Parallel Signal Processing Research on the HEP. [Citation Graph (0, 0)][DBLP ] Conf ] Gyungho Lee , Clyde P. Kruskal , David J. Kuck The Effectiveness of Automatic Restructuring on Nonnumerical Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandru Nicolau Uniform Parallelism Exploitation in Ordinary Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Aloysius K. Mok A Graph-Based Computation Model for Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] James C. Browne Formulation and Programming of Parallel Computations: A Unified Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Robert E. Strom , Shaula Yemini Synthesizing Distributed and Parallel Programs through Optimistic Transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Jouko O. Viitanen , Pertti Vanni The TAMIPS Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Dubois A Cache-Based Multiprocessor with High Efficiency. [Citation Graph (0, 0)][DBLP ] Conf ] Lee D. Coraor , Paul T. Hulina A Reconfigurable Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Händler , Erik Maehle , Klaus Wirl Dirmu Multiprocessor Configurations. [Citation Graph (0, 0)][DBLP ] Conf ] Ping-Sheng Tseng , Kai Hwang , Viktor K. Prasanna A VLSI-Based Multiprocessor Architecture for Implementing Parallel Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] James C. Browne Characterization of Parallel Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Jesus O. Tuazon , John C. Peterson , Moshe Pniel , Don Lieberman Caltech/JPL MARK II Hypercube Concurrent Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Ran Ginosar , Dwight D. Hill Design and Implementation of Switching Systems for Parallel Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Creve Maples Pyramids, Crossbars and Thousands of Processors. [Citation Graph (0, 0)][DBLP ] Conf ] William Robertson , D. Pincock , D. N. Swingler A Reconfigurable Architecture for Digital Time Domain Beamforming. [Citation Graph (0, 0)][DBLP ] Conf ] Russ Miller , Quentin F. Stout Varying Diameter and Problem Size in Mesh-Connected Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Laxmikant V. Kalé Lattice-Mesh: A Multi-Bus Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] P. S. Gopalakrishnan , I. V. Ramakrishnan , Laveen N. Kanal Computing Tree Functions on Mesh-Connected Computers. [Citation Graph (0, 0)][DBLP ] Conf ] P. S. Gopalakrishnan , I. V. Ramakrishnan , Laveen N. Kanal An Efficient Connected Components Algorithm on a Mesh-Connected Computer. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Carlson Performing Tree and Prefix Computations on Modified Mesh-Connected Parallel Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Tsair-chin Lin , Dan I. Moldovan Tradeoffs in Mapping Algorithms to Array Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Quentin F. Stout Tree-Based Graph Algorithms for Some Parallel Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Francine Berman , Michael A. Goodrich , Charles Koelbel , W. J. Robison III , Karen Showell Prep-P: A Mapping Preprocessor for CHiP Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Woei Lin , Chuan-lin Wu Design of Configuration Algorithms of Commonly-Used Topologies for a Multiprocessor : STAR. [Citation Graph (0, 0)][DBLP ] Conf ] David Y. Y. Yun , Chang Nian Zhang A Programmable Systolic Array for Arithmetic Operations in Galois Fields. [Citation Graph (0, 0)][DBLP ] Conf ] Anwar Khurshid , P. David Fisher Algorithm Implementation on Reconfigurable Mixed Systolic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Karel Culik II , Sheng Yu Translation of Systolic Algorithms between Systems of Different Topology. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory F. Pfister , William C. Brantley , David A. George , Steve L. Harvey , Wally J. Kleinfelder , Kevin P. McAuliffe , Evelin S. Melton , V. Alan Norton , Jodi Weiss The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] V. Alan Norton , Gregory F. Pfister A Methodology for Predicting Multiprocessor Performance. [Citation Graph (0, 0)][DBLP ] Conf ] William C. Brantley , Kevin P. McAuliffe , Jodi Weiss RP3 Processor-Memory Element. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory F. Pfister , V. Alan Norton "Hot Spot" Contention and Combining in Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] M. Ümit Uyar , Anthony P. Reeves Fault Reconfiguration in a Distributed MIMD Environment with a Multiusage Network. [Citation Graph (0, 0)][DBLP ] Conf ] Chita R. Das , Laxmi N. Bhuyan Computation Availability of Multiple-Bus Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Prathima Agrawal RAFT: A Recursive Algorithm for Fault Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Robert H. Halstead Jr. , Juan R. Loaiza Exception Handling in Multilisp. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Hudak , Benjamin Goldberg Efficient Distributed Evaluation of Functional Programs Using Serial Combinators. [Citation Graph (0, 0)][DBLP ] Conf ] David Hemmendinger Lazy Evaluation and Cancellation of Computations. [Citation Graph (0, 0)][DBLP ] Conf ] S. Lakshmivarahan , Sudarshan K. Dhall New Parallel Algorithms for Solving First-Order and Certain Classes of Second-Order Linear Recurrences. [Citation Graph (0, 0)][DBLP ] Conf ] John M. Marberg , Eli Gafni Sorting and Selection in Multi-Channel Broadcast Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Yijie Han A Family of Parallel Sorting Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Sai Choi Kwan , Jean-Loup Baer , G. Zick , T. Snyder Parallel Tag-Distribution Sort. [Citation Graph (0, 0)][DBLP ] Conf ] Dharma P. Agrawal , P. Ja-SongLeu , Cai TaoNie Parallel Sorting on the B-HIVE Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Pin-Yee Chen , Miguel Nussbaum Sorting with Systolic Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] 