Conferences in DBLP

Workshop on Interaction between Compilers and Computer Architectures (IEEEinteract)
2004 (conf/IEEEinteract/2004)

1. Youfeng Wu, Mauricio Breternitz Jr., Tevi Devor
   Continuous Trip Count Profiling for Loop Optimizations in Two-Phase Dynamic Binary Translato. [Citation Graph (0, 0)][DBLP]
   Interaction between Compilers and Computer Architectures, 2004, pp:3-12 [Conf]
   
2. Jan Müller, Dirk Fimmel, Renate Merker
   Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling. [Citation Graph (0, 0)][DBLP]
   Interaction between Compilers and Computer Architectures, 2004, pp:13-21 [Conf]
   
3. José Manuel Velasco, David Atienza, Francky Catthoor, Francisco Tirado, Katzalin Olcoz, Jose Manuel Mendias
   Garbage Collector Refinement for New Dynamic Multimedia Applications on Embedded Systems. [Citation Graph (0, 0)][DBLP]
   Interaction between Compilers and Computer Architectures, 2004, pp:25-32 [Conf]
   
4. José Manuel Velasco, Antonio Ortiz, Katzalin Olcoz, Francisco Tirado
   Dynamic Management of Nursery Space Organization in Generational Collection. [Citation Graph (0, 0)][DBLP]
   Interaction between Compilers and Computer Architectures, 2004, pp:33-40 [Conf]
   
5. Osman S. Unsal, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
   Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy Reduction. [Citation Graph (0, 0)][DBLP]
   Interaction between Compilers and Computer Architectures, 2004, pp:43-52 [Conf]
   
6. Gilles Pokam, François Bodin
   Energy-Efficiency Potential of a Phase-Based Cache Resizing Scheme for Embedded Systems. [Citation Graph (0, 0)][DBLP]
   Interaction between Compilers and Computer Architectures, 2004, pp:53-62 [Conf]
   
7. Peter K. Szwed, Daniel Marques, Robert M. Buels, Sally A. McKee, Martin Schulz
   SimSnap: Fast-Forwarding via Native Execution and Application-Level Checkpointing. [Citation Graph (0, 0)][DBLP]
   Interaction between Compilers and Computer Architectures, 2004, pp:65-74 [Conf]
   
8. Ravi V. Batchu, Daniel A. Jiménez
   Exploiting Procedure Level Locality to Reduce Instruction Cache Misses. [Citation Graph (0, 0)][DBLP]
   Interaction between Compilers and Computer Architectures, 2004, pp:75-84 [Conf]
   
9. Manel Fernández, Roger Espasa
   Link-Time Optimization Techniques for Eliminating Conditional Branch Redundancies. [Citation Graph (0, 0)][DBLP]
   Interaction between Compilers and Computer Architectures, 2004, pp:87-96 [Conf]
   
10. Oliverio J. Santana, Alex Ramírez, Mateo Valero
    Reducing Fetch Architecture Complexity Using Procedure Inlining. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2004, pp:97-106 [Conf]
    
11. Evangelia Athanasaki, Nectarios Koziris
    Fast Indexing for Blocked Array Layouts to Improve Multi-Level Cache Locality. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2004, pp:109-119 [Conf]
    
12. Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura
    Data Movement Optimization for Software-Controlled On-Chip Memory. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2004, pp:120-127 [Conf]