Conferences in DBLP
Francisca Quintana , Jesús Corbal , Roger Espasa , Mateo Valero Adding a vector unit to a superscalar processor. [Citation Graph (0, 0)][DBLP ] Conf ] Huy Nguyen , Lizy Kurian John Exploiting SIMD parallelism in DSP and multimedia algorithms using the AltiVec technology. [Citation Graph (0, 0)][DBLP ] Conf ] Kunle Olukotun , Lance Hammond , Mark Willey Improving the performance of speculatively parallel applications on the Hydra CMP. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey B. Rothman , Alan Jay Smith The pool of subsectors cache design. [Citation Graph (0, 0)][DBLP ] Conf ] Peter J. Keleher Symmetry and performance in consistency protocols. [Citation Graph (0, 0)][DBLP ] Conf ] F. Jesús Sánchez , Antonio González A locality sensitive multi-module cache with explicit management. [Citation Graph (0, 0)][DBLP ] Conf ] Jeeraporn Srisawat , Nikitas A. Alexandridis A new ``quad-tree-based'' sub-system allocation technique for mesh-connected parallel machines. [Citation Graph (0, 0)][DBLP ] Conf ] Andrei Radulescu , Arjan J. C. van Gemund On the complexity of list scheduling algorithms for distributed-memory systems. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Jiménez-González , Josep-Lluis Larriba-Pey , Juan J. Navarro Communication conscious radix sort. [Citation Graph (0, 0)][DBLP ] Conf ] Martin C. Rinard , Pedro C. Diniz Eliminating synchronization bottlenecks in object-based programs using adaptive replication. [Citation Graph (0, 0)][DBLP ] Conf ] Kyung Dong Ryu , Jeffrey K. Hollingsworth , Peter J. Keleher Mechanisms and policies for supporting fine-grained cycle stealing. [Citation Graph (0, 0)][DBLP ] Conf ] Dejan Perkovic , Peter J. Keleher Responsiveness without interrupts. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan C. Chou , Jason Fung , John Paul Shen Reducing branch misprediction penalties via dynamic control independence detection. [Citation Graph (0, 0)][DBLP ] Conf ] Alex Ramírez , Josep-Lluis Larriba-Pey , Carlos Navarro , Josep Torrellas , Mateo Valero Software trace cache. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Hung Chi , Jun-Li Yuan , Chin-Ming Cheung Cyclic dependence based data reference prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaowei Shen , Arvind , Larry Rudolph CACHET: an adaptive cache coherence protocol for distributed shared-memory systems. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander V. Veidenbaum , Weiyu Tang , Rajesh K. Gupta , Alexandru Nicolau , Xiaomei Ji Adapting cache line size to application behavior. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy Sherwood , Brad Calder , Joel S. Emer Reducing cache misses using hardware and software page placement. [Citation Graph (0, 0)][DBLP ] Conf ] Dongming Jiang , Brian O'Kelley , Xiang Yu , Sanjeev Kumar , Angelos Bilas , Jaswinder Pal Singh Application scaling under shared virtual memory on a cluster of SMPs. [Citation Graph (0, 0)][DBLP ] Conf ] Liviu Iftode , Matthias A. Blumrich , Cezary Dubnicki , David L. Oppenheimer , Jaswinder Pal Singh , Kai Li Shared virtual memory with automatic update support. [Citation Graph (0, 0)][DBLP ] Conf ] Evan Speight , Hazim Abdel-Shafi , John K. Bennett Realizing the performance potential of the virtual interface architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Valentin Puente , José A. Gregorio , Cruz Izu , Ramón Beivide , Fernando Vallejo Low-level router design and its impact on supercomputer system performance. [Citation Graph (0, 0)][DBLP ] Conf ] José F. Martínez , Josep Torrellas , José Duato Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity. [Citation Graph (0, 0)][DBLP ] Conf ] D. Franco , I. Garcés , Emilio Luque A new method to make communication latency uniform: distributed routing balancing. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco Corbera , Rafael Asenjo , Emilio L. Zapata New shape analysis techniques for automatic parallelization of C codes. [Citation Graph (0, 0)][DBLP ] Conf ] Amy W. Lim , Gerald I. Cheong , Monica S. Lam An affine partitioning algorithm to maximize parallelism and minimize communication. [Citation Graph (0, 0)][DBLP ] Conf ] Claudia Roberta Calidonna , Maurizio Giordano , Mario Mango Furnari A graphic parallelizing environment for user-compiler interaction. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Oguchi , Masaru Kitsuregawa Dynamic remote memory acquisition for parallel data mining on ATM-connected PC cluster. [Citation Graph (0, 0)][DBLP ] Conf ] Yong E. Cho , Marianne Winslett , Szu-Wen Kuo , Jonghyun Lee , Ying Chen Parallel I/O for scientific applications on heterogeneous clusters: a resource-utilization approach. [Citation Graph (0, 0)][DBLP ] Conf ] Shinji Sumimoto , Hiroshi Tezuka , Atsushi Hori , Hiroshi Harada , Toshiyuki Takahashi , Yutaka Ishikawa The design and evaluation of high performance communication using a Gigabit Ethernet. [Citation Graph (0, 0)][DBLP ] Conf ] Donald Yeung The scalability of multigrain systems. [Citation Graph (0, 0)][DBLP ] Conf ] Nandini Mukherjee , John R. Gurd A comparative analysis of four parallelisation schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas L. Sterling , Larry A. Bergman A design analysis of a hybrid technology multithreaded architecture for petaflops scale computation3. [Citation Graph (0, 0)][DBLP ] Conf ] Xavier Martorell , Eduard Ayguadé , Nacho Navarro , Julita Corbalán , Marc González , Jesús Labarta Thread fork/join techniques for multi-level parallelism exploitation in NUMA multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Suvas Vajracharya , Steve Karmesin , Peter H. Beckman , James Crotinger , Allen D. Malony , Sameer Shende , R. R. Oldehoeft , Stephen Smith SMARTS: exploiting temporal locality and parallelism through vertical execution. [Citation Graph (0, 0)][DBLP ] Conf ] Bradford L. Chamberlain , E. Christopher Lewis , Lawrence Snyder Problem space promotion and its evaluation as a technique for efficient parallel computation. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios S. Nikolopoulos , Theodore S. Papatheodorou A quantitative architectural evaluation of synchronization algorithms and disciplines on ccNUMA systems: the case of the SGI Origin2000. [Citation Graph (0, 0)][DBLP ] Conf ] Hongzhang Shan , Jaswinder Pal Singh A comparison of MPI, SHMEM and cache-coherent shared address space programming models on the SGI Origin2000. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi R. Iyer , Nancy M. Amato , Lawrence Rauchwerger , Laxmi N. Bhuyan Comparing the memory system performance of the HP V-class and SGI Origin 2000 multiprocessors using microbenchmarks and scientific applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan Martel , Daniel Ortega , Eduard Ayguadé , Mateo Valero Increasing effective IPC by exploiting distant parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Roth , Andreas Moshovos , Gurindar S. Sohi Improving virtual function call target prediction via dependence-based pre-computation. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro Marcuello , Antonio González Clustered speculative multithreaded processors. [Citation Graph (0, 0)][DBLP ] Conf ] Yuanyuan Zhou , Peter M. Chen , Kai Li Fast cluster failover using virtual memory-mapped communication. [Citation Graph (0, 0)][DBLP ] Conf ] Michael D. Beynon , Alan Sussman , Joel H. Saltz Performance impact of proxies in data intensive client-server applications. [Citation Graph (0, 0)][DBLP ] Conf ] A. Ferre-Vilaplana , José M. Bernabéu-Aubán A comparison of two approaches for independent scaling up of processing and communication capacities in multicomputer networks. [Citation Graph (0, 0)][DBLP ] Conf ] Glenn Reinman , Brad Calder , Dean M. Tullsen , Gary S. Tyson , Todd M. Austin Classifying load and store instructions for memory renaming. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Chen , Michael D. Smith Reorganizing global schedules for register allocation. [Citation Graph (0, 0)][DBLP ] Conf ] V. Janaki Ramanan , Ramaswamy Govindarajan Resource usage models for instruction scheduling: two new models and a classification. [Citation Graph (0, 0)][DBLP ] Conf ] John M. Mellor-Crummey , David B. Whalley , Ken Kennedy Improving memory hierarchy performance for irregular applications. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Menon , Keshav Pingali High-level semantic optimization of numerical codes. [Citation Graph (0, 0)][DBLP ] Conf ] Siddhartha Chatterjee , Vibhor V. Jain , Alvin R. Lebeck , Shyam Mundhra , Mithuna Thottethodi Nonlinear array layouts for hierarchical memory systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jay B. Brockman , Peter M. Kogge , Thomas L. Sterling , Vincent W. Freeh , Shannon K. Kuntz Microservers: a new memory semantics for massively parallel computing. [Citation Graph (0, 0)][DBLP ] Conf ] Ashley Saulsbury , Su-Jaen Huang , Fredrik Dahlgren Efficient management of memory hierarchies in embedded DRAM systems. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Molina , Antonio González , Jordi Tubella Dynamic removal of redundant computations. [Citation Graph (0, 0)][DBLP ] Conf ] Induprakas Kodukula , Keshav Pingali , Robert Cox , Dror E. Maydan An experimental evaluation of tiling and shackling for memory hierarchy management. [Citation Graph (0, 0)][DBLP ] Conf ] Jacqueline Chame , Sungdo Moon A tile selection algorithm for data locality and cache interference. [Citation Graph (0, 0)][DBLP ] Conf ] Mahmut T. Kandemir , Prithviraj Banerjee , Alok N. Choudhary , J. Ramanujam , Eduard Ayguadé An integer linear programming approach for optimizing cache locality. [Citation Graph (0, 0)][DBLP ] Conf ] 