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Conferences in DBLP

International Conference on Supercomputing (ICS) (ics)
2001 (conf/ics/2001)

  1. G. Edward Suh, Srinivas Devadas, Larry Rudolph
    Analytical cache models with applications to cache partitioning. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:1-12 [Conf]
  2. Jiajing Zhu, Jay Hoeflinger, David A. Padua
    A synthesis of memory mechanisms for distributed architectures. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:13-22 [Conf]
  3. Dimitrios S. Nikolopoulos, Eduard Ayguadé, Theodore S. Papatheodorou, Constantine D. Polychronopoulos, Jesús Labarta
    The trade-off between implicit and explicit data distribution in shared-memory programming paradigms. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:23-37 [Conf]
  4. Nikolay Mateev, Vijay Menon, Keshav Pingali
    Fractal symbolic analysis. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:38-49 [Conf]
  5. Yonghong Song, Rong Xu, Cheng Wang, Zhiyuan Li
    Data locality enhancement by memory reduction. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:50-64 [Conf]
  6. Steven J. Deitz, Bradford L. Chamberlain, Lawrence Snyder
    Eliminating redundancies in sum-of-product array computations. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:65-77 [Conf]
  7. Peng Wu, Albert Cohen, Jay Hoeflinger, David A. Padua
    Monotonic evolution: an alternative to induction variable substitution for dependence analysis. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:78-91 [Conf]
  8. Arun Chauhan, Ken Kennedy
    Optimizing strategies for telescoping languages: procedure strength reduction and procedure vectorization. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:92-101 [Conf]
  9. Daniel Cociorva, J. W. Wilkins, Chi-Chung Lam, Gerald Baumgartner, J. Ramanujam, P. Sadayappan
    Loop optimization for a class of memory-constrained computations. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:103-113 [Conf]
  10. Daniel Jiménez-González, Juan J. Navarro, Josep-Lluis Larriba-Pey
    Fast parallel in-memory 64-bit sorting. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:114-122 [Conf]
  11. Thomas Rauber, Gudula Rünger
    Optimizing locality for ODE solvers. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:123-132 [Conf]
  12. Bradford L. Chamberlain, Lawrence Snyder
    Array language support for parallel sparse computation. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:133-145 [Conf]
  13. Michel Cosnard, Laura Grigori
    A parallel algorithm for sparse symbolic LU factorization without pivoting on out-of-core matrices. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:146-153 [Conf]
  14. John M. Mellor-Crummey, Robert J. Fowler, David B. Whalley
    Tools for application-oriented performance tuning. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:154-165 [Conf]
  15. Dhruva R. Chakrabarti, Prithviraj Banerjee
    Global optimization techniques for automatic parallelization of hybrid applications. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:166-180 [Conf]
  16. Jonghyun Lee, Marianne Winslett, Xiaosong Ma, Shengke Yu
    Tuning high-performance scientific codes: the use of performance models to control resource usage during data migration and I/O. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:181-195 [Conf]
  17. Antoine Monsifrot, François Bodin
    Computer aided hand tuning (CAHT): "applying case-based reasoning to performance tuning". [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:196-203 [Conf]
  18. Nathan T. Slingerland, Alan Jay Smith
    Cache performance for multimedia applications. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:204-217 [Conf]
  19. Carlos Álvarez, Jesús Corbal, Esther Salamí, Mateo Valero
    On the potential of tolerant region reuse for multimedia applications. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:218-228 [Conf]
  20. Morgan Hirosuke Miki, Mamoru Sakamoto, Shingo Miyamoto, Yoshinori Takeuchi, Toyohiko Yoshida, Isao Shirakawa
    Evaluation of processor code efficiency for embedded systems. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:229-235 [Conf]
  21. Claude Limousin, Julien Sébot, Alexis Vartanian, Nathalie Drach-Temam
    Improving 3D geometry transformations on a simultaneous multithreaded SIMD processor. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:236-245 [Conf]
  22. H. Martin Bücker, Bruno Lang, Dieter an Mey, Christian H. Bischof
    Bringing together automatic differentiation and OpenMP. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:246-251 [Conf]
  23. Paul van der Mark, Gerard Cats, Lex Wolters
    Automatic code generation for a turbulence scheme. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:252-259 [Conf]
  24. Constantine Bekas, Effrosini Kokiopoulou, I. Koutis, Efstratios Gallopoulos
    Towards the effective parallel computation of matrix pseudospectra. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:260-269 [Conf]
  25. Dany Mezher
    A graphical tool for driving the parallel computation of pseudosprectra. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:270-276 [Conf]
  26. Vivek Sarkar, Mauricio J. Serrano, Barbara B. Simons
    Register-sensitive selection, duplication, and sequencing of instructions. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:277-288 [Conf]
  27. Soner Önder, Rajiv Gupta
    Load and store reuse using register file contents. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:289-302 [Conf]
  28. Julita Corbalán, Xavier Martorell, Jesús Labarta
    Improving Gang Scheduling through job performance analysis and malleability. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:303-311 [Conf]
  29. Ramon Canal, Antonio González
    Reducing the complexity of the issue logic. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:312-320 [Conf]
  30. Andreas Moshovos, Dionisios N. Pnevmatikatos, Amirali Baniasadi
    Slice-processors: an implementation of operation-based prediction. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:321-334 [Conf]
  31. Jin-Soo Kim, Kangho Kim, Sung-In Jung
    Building a high-performance communication layer over virtual interface architecture on Linux clusters. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:335-347 [Conf]
  32. Matt Postiff, David Greene, Steven Raasch, Trevor N. Mudge
    Integrating superscalar processor components to implement register caching. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:348-357 [Conf]
  33. Mark N. Yankelevsky, Constantine D. Polychronopoulos
    alpha-coral: a multigrain, multithreaded processor architecture. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:358-367 [Conf]
  34. Chong-liang Ooi, Seon Wook Kim, Il Park, Rudolf Eigenmann, Babak Falsafi, T. N. Vijaykumar
    Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:368-380 [Conf]
  35. Hong Tang, Tao Yang
    Optimizing threaded MPI execution on SMP clusters. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:381-392 [Conf]
  36. George S. Almasi, Calin Cascaval, José G. Castaños, Monty Denneau, Wilm E. Donath, Maria Eleftheriou, Mark Giampapa, C. T. Howard Ho, Derek Lieber, José E. Moreira, Dennis M. Newns, Marc Snir, Henry S. Warren Jr.
    Demonstrating the scalability of a molecular dynamics application on a Petaflop computer. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:393-406 [Conf]
  37. Tzvetan Ostromsky, Wojciech Owczarz, Zahari Zlatev
    Computational challenges in large-scale air pollution modelling. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:407-418 [Conf]
  38. Claudia Roberta Calidonna, Claudia Di Napoli, Maurizio Giordano, Mario Mango Furnari, Salvatore Di Gregorio
    A network of cellular automata for a landslide simulation. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:419-426 [Conf]
  39. Ramesh Radhakrishnan, Ravi Bhargava, Lizy Kurian John
    Improving Java performance using hardware translation. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:427-439 [Conf]
  40. Pramod G. Joisha, Samuel P. Midkiff, Mauricio J. Serrano, Manish Gupta
    A framework for efficient reuse of binary code in Java. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:440-453 [Conf]
  41. Richard Tran Mills, Andreas Stathopoulos, Evgenia Smirni
    Algorithmic modifications to the Jacobi-Davidson parallel eigensolver to dynamically balance external CPU and memory load. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:454-463 [Conf]
  42. Sergio Briguglio, Beniamino Di Martino, Gregorio Vlad
    Workload decomposition for particle simulation applications on hierarchical distributed-shared memory parallel systems with integration of HPF and OpenMP. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:464- [Conf]
  43. Nancy Tran, Daniel A. Reed
    ARIMA time series modeling and forecasting for adaptive I/O prefetching. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:473-485 [Conf]
  44. Abdel-Hameed A. Badawy, Aneesh Aggarwal, Donald Yeung, Chau-Wen Tseng
    Evaluating the impact of memory system performance on software prefetching and locality optimizations. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:486-500 [Conf]
  45. Daniel Ortega, Mateo Valero, Eduard Ayguadé
    A novel renaming mechanism that boosts software prefetching. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:501-510 [Conf]
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for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002