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Conferences in DBLP

Synthesis for Control Dominated Circuits (ifip10-2)
1992 (conf/ifip10-2/1992)

  1. ChiLai Huang, Joseph Lis, Michael Quayle, Saurin Shroff
    RTL Controller Synthesis. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:3-17 [Conf]
  2. Steve C.-Y. Huang, Wayne Wolf
    Timing-Driven State Assignment for Controller-Datapath Systems. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:19-31 [Conf]
  3. Alan J. Coppola, Marek A. Perkowski, Robert Anderson, Jeffrey S. Freedman, Edmund Pierzchala
    Tokenized State Machine Model for Synthesis of Sequential Circuits into EPLDs and FPGAs. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:33-46 [Conf]
  4. L. Gerbaux, Régis Leveugle, Gabriele Saucier
    Synthesis of large controllers using ROM or PLA generators. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:47-59 [Conf]
  5. Augusli Kifli, R. De Wulf, J. Zegers, Gert Goossens, Paul Six, Hugo De Man
    Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:61-71 [Conf]
  6. James Pardey
    The Synthesis of a Parallel Controller from a Petri Net Model. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:73-89 [Conf]
  7. H. Belhadj, L. Gerbaux, Marie-Claude Bertrand, Gabriele Saucier
    Specification and Synthesis of Communicating Finite State Machines. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:91-102 [Conf]
  8. Jochen Beister, Ralf Wollowski
    Controller Implementation by Communicating Asynchronous Sequential Circuits Generated from a Petri Net Specification of Required Behavior. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:103-115 [Conf]
  9. Amnon Baron Cohen, Michael Shechory
    Pathway: A datapath layout assembler. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:119-131 [Conf]
  10. Lotfi Ben Ammar, Alain Greiner
    FITPATH: A Process-Independent Datapath Compiler Providing High Density Layout. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:133-151 [Conf]
  11. Régis Leveugle, C. Safina
    Generation of optimized datapaths: bit-slice versus standard cells. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:153-166 [Conf]
  12. Evagelos Katsadas, Z. Sahraoui, M. Wouters, Veerle Derudder, Ivo Bolsens, Paul Six, Hugo De Man
    Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:167-181 [Conf]
  13. Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura
    Design of data-path module generators from algorithmic representations. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:183-192 [Conf]
  14. Farhad Mavaddat
    Data-Path Synthesis as Grammar Inference. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:193-205 [Conf]
  15. E. T. Kapuya, M. D. Edwards
    Microarchitecture/Microcode Synthesis from VHDL. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:209-218 [Conf]
  16. I. Park, Kevin O'Brien, Ahmed Amine Jerraya
    AMICAL: Architectural Synthesis based on VHDL. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:219-234 [Conf]
  17. Yang Wu, Ian Dorrington
    RTL OptimizA: From Control Data Flow Graph to Logic Circuit. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:235-247 [Conf]
  18. Peter Marwedel
    Implementations of IF-statements in the TODOS microarchitecture synthesis system. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:249-262 [Conf]
  19. J. Biesenack, Norbert Wehn, A. Stoll, Michael Payer
    Data Part Optimizations in the CALLAS Synthesis Environment. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:263-274 [Conf]
  20. Anne Mignotte, Marie-Claude Bertrand, Michel Crastes de Paulet, Jérôme Rampon, Gabriele Saucier
    ASYL: A Control Driven RTL Synthesis System using Library Blocks. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:275-291 [Conf]
  21. C. Safina, Régis Leveugle
    Clocking scheme selection for circuits made up of a controller and a datapath. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:293-308 [Conf]
  22. Francesco Curatelli, Daniele D. Caviglia, Marco Chirico, Giacomo M. Bisio
    Optimization strategies in symbolic compaction. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:311-322 [Conf]
  23. H. Zhang, Kunihiro Asada
    A general and efficient mask pattern generator for non-series-parallel CMOS transistor network. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:323-333 [Conf]
  24. Pierre Abouzeid, Régis Leveugle, Gabriele Saucier
    Logic Synthesis for Automatic Layout. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:335-343 [Conf]
  25. Eric Gautrin, Laurent Perraudeau
    MADMACS: an environment for the layout of regular arrays. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:345-358 [Conf]
  26. J. F. M. Theeuwen, H. M. A. M. Arts, Jos T. J. van Eijndhoven, H. J. H. Sleuters, J. H. P. Wijdeven
    Module Generation in an Architectural Synthesis Environment. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:359-371 [Conf]
  27. Andreas Münzner
    BADGE - A synthesis tool for customized arithmetic building blocks. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:373-384 [Conf]
  28. A. G. Jost, L. F. Wang, S. Periyalwar, William Robertson
    Automatic Layout Synthesis of Pipelined Multipliers for Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:385-398 [Conf]
  29. A. J. W. M. ten Berg
    Floorplan Optimized Topological Partitioning of Programmed Logic Arrays. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:399-411 [Conf]
  30. Antonio Martinez
    Timing Model Accuracy Issues and Automated Library Characterization. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:413-426 [Conf]
  31. B. Conq, R. Etienne, T. Perez-Segovia
    Design Library Portability: A Case Study. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:427-436 [Conf]
  32. Daniel Gajski, Nikil D. Dutt
    Benchmarking and the Art of Syntesis Tool Comparison. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:439-453 [Conf]
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