Conferences in DBLP

Synthesis for Control Dominated Circuits (ifip10-2)
1992 (conf/ifip10-2/1992a)

1. James B. Saxe, Stephen J. Garland, John V. Guttag, James J. Horning
   Using Transformations and Verification in Ciruit Design. [Citation Graph (0, 0)][DBLP]
   Designing Correct Circuits, 1992, pp:1-25 [Conf]
   
2. Jo C. Ebergen, Ad M. G. Peeters
   Modulo-N Counters: Design and Analysis of Delay-Insensitive Circuits. [Citation Graph (0, 0)][DBLP]
   Designing Correct Circuits, 1992, pp:27-46 [Conf]
   
3. Michael Mendler, Terry Stroup
   Newtonian Arbiters Cannot be Proven Correct. [Citation Graph (0, 0)][DBLP]
   Designing Correct Circuits, 1992, pp:47-66 [Conf]
   
4. Stefan Krischer
   Incomplete TRS-Specifications of Boolean Functions and their Verification. [Citation Graph (0, 0)][DBLP]
   Designing Correct Circuits, 1992, pp:67-79 [Conf]
   
5. Ghislaine Thuau, Bachir Berkane
   Using the Language Lustre for Sequential Circuit Verification. [Citation Graph (0, 0)][DBLP]
   Designing Correct Circuits, 1992, pp:81-96 [Conf]
   
6. Peter Naur
   Invited talk: Three Notions of Proof. [Citation Graph (0, 0)][DBLP]
   Designing Correct Circuits, 1992, pp:97-101 [Conf]
   
7. Guy Durrieu, Kamel Kessaci, Michel Lemaître
   Transe: An Experimental Transformation Assistant for Digital Circuit Design. [Citation Graph (0, 0)][DBLP]
   Designing Correct Circuits, 1992, pp:103-118 [Conf]
   
8. Satnam Singh
   Circuit Analysis by Non-Standard Interpretation. [Citation Graph (0, 0)][DBLP]
   Designing Correct Circuits, 1992, pp:119-138 [Conf]
   
9. Björn Lisper, Sanjay V. Rajopadhye
   Reasoning about Permutations in Regular Arrays. [Citation Graph (0, 0)][DBLP]
   Designing Correct Circuits, 1992, pp:139-157 [Conf]
   
10. Lars Rossen, Robin Sharp
    Sequence Semantics of Ruby. [Citation Graph (0, 0)][DBLP]
    Designing Correct Circuits, 1992, pp:159-171 [Conf]
    
11. Diederik Verkest, Luc J. M. Claesen, Hugo De Man
    A Proof of the Non-Restoring Division Algorithm and its Implementation on the Cathedral-II ALU. [Citation Graph (0, 0)][DBLP]
    Designing Correct Circuits, 1992, pp:173-192 [Conf]
    
12. Jörg Bormann, H. Nusser-Wehlan, Gerd Venzl
    Invited Talk: Formal Design in an Industrial Research Laboratory: Lessons and Perspectives. [Citation Graph (0, 0)][DBLP]
    Designing Correct Circuits, 1992, pp:193-213 [Conf]
    
13. Mark R. Greenstreet
    Using Synchronized Transitions for Simulation and Timing Verification. [Citation Graph (0, 0)][DBLP]
    Designing Correct Circuits, 1992, pp:215-236 [Conf]
    
14. Scott F. Smith, Amy E. Zwarico
    Provably Correct Synthesis of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    Designing Correct Circuits, 1992, pp:237-260 [Conf]
    
15. Mark B. Josephs, Rudolf H. Mak, Jan Tijmen Udding, Tom Verhoeff, Jelio T. Yantchev
    High-Level Design of an Asynchronous Packet-Routing Chip. [Citation Graph (0, 0)][DBLP]
    Designing Correct Circuits, 1992, pp:261-274 [Conf]
    
16. Michael Kishinevsky, Alex Kondratyev, Alexander Taubin, Victor Varshavsky
    Analysis and Identification of Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    Designing Correct Circuits, 1992, pp:275-287 [Conf]