The SCEAS System
Navigation Menu

Conferences in DBLP

IFIP WG10.3 Publications (ifip10-3)
1993 (conf/ifip10-3/1993)

  1. Jiang Wang, Christine Eisenbeis
    Decomposed Software Pipelining: A New Approach to Exploit Instruction Level Parallelism for Loop Programs. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:3-14 [Conf]
  2. Vicki H. Allan, M. Rajagopalan, Randall M. Lee
    Software Pipelining: Petri Net Pacemaker. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:15-26 [Conf]
  3. A. Zaafrani, Mabo Robert Ito
    Efficient Execution of Doacross Loops on Distributed Memory Systems. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:27-38 [Conf]
  4. Chris J. Newburn, Andrew S. Huang, John Paul Shen
    Balancing Fine- and Medium-Grained Parallelism in Scheduling Loops for the XIMD Architecture. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:39-52 [Conf]
  5. Shaw-Yen Tseng, Chung-Ta King, Chuan Yi Tang
    A New Loop Partition Method-Clustering. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:53-64 [Conf]
  6. Takayoshi Iitsuka
    Flow-sensitive Interprocedural Analysis Method for Parallelization. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:65-76 [Conf]
  7. Stephan Murer, Philipp Färber
    Code Generation for Multi-Threaded Architectures from Dataflow Graphs. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:77-90 [Conf]
  8. Walid A. Najjar, Lucas Roh, A. P. Wim Böhm
    The Initial Performance of a Bottom-Up Clustering Algorithm for Dataflow Graphs. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:91-100 [Conf]
  9. H. Seebauer, Jörg Siemers
    Synchronization and Parallelism Control in the BARDE Dataflow Processor. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:105-116 [Conf]
  10. Kentaro Shimada, Hanpei Koike, Hidehiko Tanaka
    The Instruction Set Architecture of the Inference Processor UNIRED II. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:117-128 [Conf]
  11. Jocelyn Sérot, Georges Quénot, Bertrand Zavidovique
    A Functional Data-flow Architecture Dedicated to Real-time Image Processing. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:129-140 [Conf]
  12. William G. Farquhar, Paraskevas Evripidou
    DART: A Data-Driven Processor Architecture for Real-Time Computing. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:141-152 [Conf]
  13. David E. Culler, Klaus E. Schauser, Thorsten von Eicken
    Two Fundamental Limits on Dataflow Multiprocessing. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:153-164 [Conf]
  14. Thomas L. Sterling, Michael J. MacDonald
    The Realities of Parallel Processing and Dataflow's Role in It: Lessons from the NASA HPCC Program. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:165-176 [Conf]
  15. Jon A. Solworth, Jerry Stamatopoulos
    Integrated Network Barriers for D-Dimensional Meshes. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:179-190 [Conf]
  16. Shahram Latifi
    Parallel Dimension Permutations on Star-Graph. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:191-201 [Conf]
  17. Rajendra V. Boppana
    On the Effectiveness of Interleaved Memories for Binary Trees. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:203-214 [Conf]
  18. G. Menez, Michel Auguin, Fernand Boéri, C. Carrière
    Contribution of Compilation Techniques to the Synthesis of Dedicated VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:217-228 [Conf]
  19. Soo-Mook Moon, Kemal Ebcioglu, Ashok K. Agrawala
    Selective Scheduling Framework for Speculative Operations in VLIW and Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:229-242 [Conf]
  20. David A. Berson, Rajiv Gupta, Mary Lou Soffa
    URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:243-254 [Conf]
  21. Norman Rubin
    Data Flow Computing and the Conjugate Gradient Method. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:257-264 [Conf]
  22. Marc Daumas, Paraskevas Evripidou
    Results of Parallel Implementations of the Selection Problem Using Sisal. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:265-272 [Conf]
  23. Andrew Sohn
    A Parallel Implementation of the Traveling Salesman Problem on a Sequent Symmetry Mulitprocessor. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:273-280 [Conf]
  24. Andrew L. Wendelborn, H. Garsden
    Exploring the Stream Data Type in SISAL and Other Languages. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:283-294 [Conf]
  25. Edward A. Lee
    Mulitdimensional Streams Rooted in Dataflow. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:295-306 [Conf]
  26. Ciaran O'Donnell
    High Level Compiling for Low Level Machines. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:309-320 [Conf]
  27. Ali-Reza Adl-Tabatabai, Thomas R. Gross, Guei-Yuan Lueh, James Reinders
    Modeling Instruction-Level Parallelism for Software Pipelining. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:321-330 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002