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Conferences in DBLP

IFIP WG10.5 (ifip10-5)
1999 (conf/ifip10-5/1999)

  1. Shenggao Li, Yue Wu, Chunlei Shi, Mohammed Ismail
    Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:1-10 [Conf]
  2. G. B. Jackson, S. V. Awsare, L. D. Engh, M. A. Hemming, P. Holzmann, O. C. Kao, C. Mai-Liu, C. R. Palmer, A. Raina
    An Analog Non-Volatile Storage System for Audio Signals with Signal Conditioning for Mobile Communication Devices. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:11-22 [Conf]
  3. Bingxin Li, Hannu Tenhunen
    A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS Process. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:23-34 [Conf]
  4. Yue Wu, Shenggao Li, Mohammed Ismail, Hakan Olsson
    A Lower Power CMOS Micromixer for GHz Wireless Applications. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:35-46 [Conf]
  5. S. S. Rajput, S. S. Jamuar
    High Current, Low Voltage Current Mirrors and Applications. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:47-60 [Conf]
  6. Yue Wu, Hong-sun Kim, Fredrik Jonsson, Mohammed Ismail, Hakan Olsson
    Nonlinearity Analysis of a Short Channel CMOS Circuit for RFIC Applications. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:61-68 [Conf]
  7. Nasser Masoumi, Mohamed I. Elmasry, Safieddin Safavi-Naeini
    A Fast Parametric Model for Contact-Substrate Coupling. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:69-76 [Conf]
  8. Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie
    A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:77-88 [Conf]
  9. A. M. Rassau, G. Alagoda, David Lucas, J. Austin-Crowe, Kamran Eshraghian
    Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:89-100 [Conf]
  10. Camille Diou, Lionel Torres, Michel Robert
    Implementation of a Wavelet Transform Architecture for Image Processing. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:101-112 [Conf]
  11. Abdellah Touhafi, Wouter Brissinck, Erik F. Dirkx
    Scalable Run Time Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:113-124 [Conf]
  12. Russell Tessier
    Frontier: A Fast Placement System for FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:125-136 [Conf]
  13. Nuno Lau, Valery Sklyarov
    Dynamically Reconfigurable Implementation of Control Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:137-148 [Conf]
  14. R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili
    An IEEE Compliant Floating Point MAF. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:149-160 [Conf]
  15. C. Ninos, Haridimos T. Vergos, Dimitris Nikolos
    Design and Analysis of On-Chip CPU Pipelined Caches. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:161-172 [Conf]
  16. João M. S. Alcântara, Sergio C. Salomão, Edson do Prado Granja, Vladimir Castro Alves, Felipe M. G. França
    Synchronous to Asynchronous Conversion - A Case Study: the Blowfish Algorithm Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:173-180 [Conf]
  17. Rui L. Aguiar, Dinis M. Santos
    Clock Distribution Strategy for IP-based Development. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:181-191 [Conf]
  18. David H. Albonesi
    An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:192-205 [Conf]
  19. Mihai Munteanu, Peter A. Ivey, N. Luke Seed, Marios Psilogeorgopoulos, Neil Powell, Istvan Bogdan
    Single Ended Pass-Transistor Logic - A Comparison with CMOS and CPL. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:206-218 [Conf]
  20. Abdoul Rjoub, Odysseas G. Koufopavlou
    Multithreshold Voltage Technology for Low Power Bus Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:219-232 [Conf]
  21. Antônio Mota, Nuno Ferreira, Arlindo L. Oliveira, José C. Monteiro
    Integrating Dynamic Power Management in the Design Flow. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:233-244 [Conf]
  22. Stefan Lachowicz, Kamran Eshraghian, Hans-Jörg Pfleiderer
    Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:245-256 [Conf]
  23. José T. de Sousa
    On Defect-Level Estimation and the Clustering Effect. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:257-268 [Conf]
  24. J. Soares Augusto, C. F. Beltrá Almeida
    FASTNR: an Efficient Fault Simulator for Linear and Nonlinear DC Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:269-280 [Conf]
  25. Raimund Ubar, Dominique Borrione
    Design Error Diagnosis in Digital Circuits without Error Model. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:281-292 [Conf]
  26. Bogdan Tutuianu, Daksh Lehther, Madhulima Pandey, Ross Baldick
    Efficient RLC Macromodels for Digital IC Interconnect. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:293-304 [Conf]
  27. Alex Doboli, Ranga Vemuri
    A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:305-317 [Conf]
  28. Adrián Núñez-Aldana, Ranga Vemuri
    A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:318-32 [Conf]
  29. Augusto Gallegos, Philippe Silvestre, Michel Robert, Daniel Auvergne
    RF Interface Design Using Mixed-Mode Methodology. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:326-333 [Conf]
  30. Rolf Drechsler, Wolfgang Günther
    History-Based Dynamic Minimization During BDD Construction. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:334-345 [Conf]
  31. Luca P. Carloni, Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:346-361 [Conf]
  32. Joonyoung Kim, João P. Marques Silva, Karem A. Sakallah
    Satisfiability-Based Functional Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:362-372 [Conf]
  33. Tomohiro Yoneda
    Verification of Abstracted Instruction Cache of TITAC2: A Case Study. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:373-384 [Conf]
  34. Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita
    Speeding Up Look-up-Table Driven Logic Simulation. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:385-397 [Conf]
  35. Tom Chen, Isabelle Munn, Anneliese von Mayrhauser, Amjad Hajjar
    Efficient Verification of Behavioral Models Using Sequential Sampling Technique. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:398-406 [Conf]
  36. S. Raimbault, Gilles Sassatelli, Gamille Cambon, Michel Robert, Sébastien Pillement, Lionel Torres
    Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:407-414 [Conf]
  37. Fernando Moraes, Michel Robert, Daniel Auvergne
    A Virtual CMOS Library Approach for East Layout Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:415-426 [Conf]
  38. Ananth Durbha, Srinivas Katkoori
    RT-level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:427-438 [Conf]
  39. Fernanda Lima, Marcelo O. Johann, José Luís Almada Güntzel, Eduardo D'Avila, Luigi Carro, Ricardo Augusto da Luz Reis
    Designing a Mask Programmable Matrix for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:439-446 [Conf]
  40. Stefan Thomas Obenaus, Ted H. Szymanski
    Placements Benchmarks for 3-D VLSI. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:447-455 [Conf]
  41. Edoardo Charbon, Joel R. Phillips
    Substrate Noise: Analysis, Models, and Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:456-472 [Conf]
  42. Marcio Yukio Teruya, Marius Strum, Wang Jiang Chau
    Architectural Transformations for Hierarchical Algorithmic Descriptions. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:473-484 [Conf]
  43. João M. P. Cardoso, Horácio C. Neto
    An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:485-496 [Conf]
  44. Flávio Rech Wagner, Márcio Oyamada, Luigi Carro, Márcio Eduardo Kreutz
    Object-Oriented Modeling and Co-Simulation of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:497-508 [Conf]
  45. Christophe Jégo, Emmanuel Casseau, Eric Martin
    Architectural Synthesis with Interconnection Cost Control. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:509-520 [Conf]
  46. R. Lerch, M. Kaltenbacher, H. Landes
    CAE Environment for Electromechanical Microsystems. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:521-532 [Conf]
  47. Rainer Brück, Andreas Priebe, Kai Hahn
    Cost Consideration for Application Specific Microsystems Physical Design Stages - A New Approach for Microtechnological Process Design. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:533-543 [Conf]
  48. K. Liateni, D. Moulinier, B. Affour, A. Delpoux, Jean-Michel Karam
    Moving MEMS into Mainstream Applications: The MEMSCAP Solution. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:544-556 [Conf]
  49. Joel R. Phillips, Dan Feng
    Trends in RF Simulation Algorithms. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:557-568 [Conf]
  50. Franz Sischka
    Device Modeling and Measurement for RF Systems. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:569-582 [Conf]
  51. Alexandro M. S. Adário, Sergio Bampi
    Reconfigurable Computing: Viable Applications and Trends. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:583-594 [Conf]
  52. James C. Hoe, Arvind
    Hardware Synthesis from Term Rewriting Systems. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:595-619 [Conf]
  53. Maria-Cristina V. Marinescu, Martin C. Rinard
    A Synthesis Algorithm for Modular Design of Pipelined Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:620-635 [Conf]
  54. B. F. Romanowicz, M. H. Zaman, S. F. Bart, V. L. Rabinovich, I. Tchertkov, C. Hsu, John R. Gilbert
    A Methodology and Associated CAD Tools for Support of Concurrent Design of MEMS. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:636-648 [Conf]
  55. Martin G. Walker, Keh-Jeng Chang, Christophe J. Bianchi
    SIPPs, Why Do We Need a New Standard for Interconnect Process Parameters? [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:649-658 [Conf]
  56. Andreas Kirschbaum, Jürgen Becker, Manfred Glesner
    ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:659-670 [Conf]
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