Conferences in DBLP

IFIP WG10.5 (ifip10-5)
1993 (conf/ifip10-5/1993)

1. Kees van Berkel
   VLSI Programming of a Modulo-N Counter with Constant Response Time and Constant Power. [Citation Graph (0, 0)][DBLP]
   Asynchronous Design Methodologies, 1993, pp:1-11 [Conf]
   
2. Marly Roncken, Ronald Saeijs
   Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy. [Citation Graph (0, 0)][DBLP]
   Asynchronous Design Methodologies, 1993, pp:13-27 [Conf]
   
3. Ilana David, Ran Ginosar, Michael Yoeli
   Self-Timed Architecture of a Reduced Instruction Set Computer. [Citation Graph (0, 0)][DBLP]
   Asynchronous Design Methodologies, 1993, pp:29-43 [Conf]
   
4. O. Salomon, Heinrich Klar
   Self-Timed Fully Pipelined Multipliers. [Citation Graph (0, 0)][DBLP]
   Asynchronous Design Methodologies, 1993, pp:45-55 [Conf]
   
5. Rix Groenboom, Mark B. Josephs, Paul G. Lucassen, Jan Tijmen Udding
   Normal Form in a Delay-Insensitive Algebra. [Citation Graph (0, 0)][DBLP]
   Asynchronous Design Methodologies, 1993, pp:57-70 [Conf]
   
6. Alexandre Yakovlev, A. I. Petrov, Leonid Ya. Rosenblum
   Synthesis of Asynchronous Control Circuits from Symbolic Signal Transition Graphs. [Citation Graph (0, 0)][DBLP]
   Asynchronous Design Methodologies, 1993, pp:71-85 [Conf]
   
7. Meng-Lin Yu, P. A. Subrahmanyam
   Hazard-Free Asynchronous Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
   Asynchronous Design Methodologies, 1993, pp:87-105 [Conf]
   
8. Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
   Automated Synthesis of Asynchronous Interface Circuits. [Citation Graph (0, 0)][DBLP]
   Asynchronous Design Methodologies, 1993, pp:107-121 [Conf]
   
9. Mark B. Josephs, Jan Tijmen Udding
   Implementing a Stack as a Delay-insensitive Circuit. [Citation Graph (0, 0)][DBLP]
   Asynchronous Design Methodologies, 1993, pp:123-135 [Conf]
   
10. Jo C. Ebergen, P. F. Bertrand, S. Gingras
    Solving a Mutual Exclusion Problem with the RGD Arbiter. [Citation Graph (0, 0)][DBLP]
    Asynchronous Design Methodologies, 1993, pp:137-147 [Conf]
    
11. Jaco Haans, Kees van Berkel, Ad M. G. Peeters, Frits D. Schalij
    Asynchronous Multipliers as Combinational Handshake Circuits. [Citation Graph (0, 0)][DBLP]
    Asynchronous Design Methodologies, 1993, pp:149-163 [Conf]
    
12. Jens Sparsø, Christian D. Nielsen, Lars S. Nielsen, Jørgen Staunstrup
    Design of Self-timed Multipliers: A Comparison. [Citation Graph (0, 0)][DBLP]
    Asynchronous Design Methodologies, 1993, pp:165-179 [Conf]
    
13. Jim D. Garside
    A CMOS VLSI Implementation of an Asynchronous ALU. [Citation Graph (0, 0)][DBLP]
    Asynchronous Design Methodologies, 1993, pp:181-192 [Conf]
    
14. Al Davis, Bill Coates, Ken Stevens
    Automatic Synthesis of Fast Compact Asynchronous Control Circuits. [Citation Graph (0, 0)][DBLP]
    Asynchronous Design Methodologies, 1993, pp:193-207 [Conf]
    
15. Kees van Berkel, Ronan Burgess, Joep L. W. Kessels, Marly Roncken, Frits D. Schalij
    Characterization and Evaluation of a Compiled Asynchronous IC. [Citation Graph (0, 0)][DBLP]
    Asynchronous Design Methodologies, 1993, pp:209-221 [Conf]