Conferences in DBLP
Message from the Program Chair. [Citation Graph (0, 0)][DBLP ] Conf ] Message from the General Chair. [Citation Graph (0, 0)][DBLP ] Conf ] Tutorials and Workshops. [Citation Graph (0, 0)][DBLP ] Conf ] Reviewers. [Citation Graph (0, 0)][DBLP ] Conf ] Committees. [Citation Graph (0, 0)][DBLP ] Conf ] Justin R. Rattner Multi-Core to the Masses. [Citation Graph (0, 0)][DBLP ] Conf ] Erez Perelman , Trishul M. Chilimbi , Brad Calder Variational Path Profiling. [Citation Graph (0, 0)][DBLP ] Conf ] Sriraman Tallam , Rajiv Gupta , Xiangyu Zhang Extended Whole Program Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Changpeng Fang , Steve Carr , Soner Önder , Zhenlin Wang Instruction Based Memory Distance Analysis and its Application. [Citation Graph (0, 0)][DBLP ] Conf ] Hussam Mousa , Chandra Krintz HPS: Hybrid Profiling Support. [Citation Graph (0, 0)][DBLP ] Conf ] John D. Davis , James Laudon , Kunle Olukotun Maximizing CMP Throughput with Mediocre Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Austen McDonald , JaeWoong Chung , Hassan Chafi , Chi Cao Minh , Brian D. Carlstrom , Lance Hammond , Christos Kozyrakis , Kunle Olukotun Characterization of TCC on Chip-Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas F. Wenisch , Stephen Somogyi , Nikolaos Hardavellas , Jangwoo Kim , Chris Gniady , Anastassia Ailamaki , Babak Falsafi Store-Ordered Streaming of Shared Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Weifeng Zhang , Brad Calder , Dean M. Tullsen An Event-Driven Multithreaded Dynamic Optimization Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Yonghong Song , Spiros Kalogeropulos , Partha Tirumalai Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy M. Jones , Michael F. P. O'Boyle , Jaume Abella , Antonio González , Oguz Ergin Compiler Directed Early Register Release. [Citation Graph (0, 0)][DBLP ] Conf ] Masayo Haneda , Peter M. W. Knijnenburg , Harry A. G. Wijshoff Automatic Selection of Compiler Options Using Non-parametric Inferential Statistics. [Citation Graph (0, 0)][DBLP ] Conf ] Swarup Kumar Sahoo , Gagan Agrawal Data Centric Transformations on Non-Integer Iteration Spaces. [Citation Graph (0, 0)][DBLP ] Conf ] Konstantinos Kyriakopoulos , Kleanthis Psarris Efficient Techniques for Advanced Data Dependence Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Guy L. Steele Jr. Parallel Programming and Parallel Abstractions in Fortress. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre E. Eichenberger , Kathryn M. O'Brien , Kevin O'Brien , Peng Wu , Tong Chen , Peter H. Oden , Daniel A. Prener , Janice C. Shepherd , Byoungro So , Zehra Sura , Amy Wang , Tao Zhang , Peng Zhao , Michael Gschwind Optimizing Compiler for the CELL Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Ben Wun , Jeremy Buhler , Patrick Crowley Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Changhao Jiang , Marc Snir Automatic Tuning Matrix Multiplication Performance on Graphics Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Hongtao Zhong , Kevin Fan , Scott A. Mahlke , Michael S. Schlansker A Distributed Control Path Architecture for VLIW Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Enric Gibert , Jaume Abella , F. Jesús Sánchez , Xavier Vera , Antonio González Variable-Based Multi-module Data Caches for Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Nathan L. Binkert , Lisa R. Hsu , Ali G. Saidi , Ronald G. Dreslinski , Andrew L. Schultz , Steven K. Reinhardt Performance Analysis of System Overheads in TCP/IP Workloads. [Citation Graph (0, 0)][DBLP ] Conf ] Huiyang Zhou Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window. [Citation Graph (0, 0)][DBLP ] Conf ] Gabriel H. Loh A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Behar , Avi Mendelson , Avinoam Kolodny Trace Cache Sampling Filter. [Citation Graph (0, 0)][DBLP ] Conf ] Wei-Yu Chen , Costin Iancu , Katherine A. Yelick Communication Optimizations for Fine-Grained UPC Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Costin Iancu , Parry Husbands , Paul Hargrove HUNTing the Overlap. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Carribault , Albert Cohen , William Jalby Deep Jam: Conversion of Coarse-Grain Parallelism to Instruction-Level and Vector Parallelism for Irregular Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Moshovos , Alexandros Kostopoulos Memory State Compressors for Giga-Scale Checkpoint/Restore. [Citation Graph (0, 0)][DBLP ] Conf ] M. Wasiur Rashid , Edwin J. Tan , Michael C. Huang , David H. Albonesi Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Lian Li 0002 , Lin Gao 0002 , Jingling Xue Memory Coloring: A Compiler Approach for Scratchpad Memory Management. [Citation Graph (0, 0)][DBLP ] Conf ] Calin Cascaval , Evelyn Duesterwald , Peter F. Sweeney , Robert W. Wisniewski Multiple Page Size Modeling and Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Ilya Ganusov , Martin Burtscher Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] 