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Conferences in DBLP

Intelligent Memory Systems (ims)
2000 (conf/ims/2000)

  1. Junji Ogawa, Mark Horowitz
    A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:1-14 [Conf]
  2. Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku
    Software Controlled Reconfigurable On-Chip Memory for High Performance Computing. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:15-32 [Conf]
  3. Robert Cooksey, Dennis Colarelli, Dirk Grunwald
    Content-Based Prefetching: Initial Results. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:33-55 [Conf]
  4. Lixin Zhang, Venkata K. Pingali, Bharat Chandramouli, John B. Carter
    Memory System Support for Dynamic Cache Line Assembly. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:56-70 [Conf]
  5. Yan Solihin, Jaejin Lee, Josep Torrellas
    Adaptively Mapping Code in an Intelligent Memory Architecture. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:71-84 [Conf]
  6. Richard C. Murphy, Peter M. Kogge, Arun Rodrigues
    The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:85-103 [Conf]
  7. Mary W. Hall, Craig S. Steele
    Memory Management in a PIM-Based Architecture. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:104-121 [Conf]
  8. David Judd, Katherine A. Yelick, Christoforos E. Kozyrakis, David Martin, David A. Patterson
    Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:122-134 [Conf]
  9. Csaba Andras Moritz, Matthew Frank, Saman P. Amarasinghe
    FlexCache: A Framework for Flexible Compiler Generated Data Caching. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:135-146 [Conf]
  10. Peter Grun, Nikil D. Dutt, Alexandru Nicolau
    Aggressive Memory-Aware Compilation. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:147-151 [Conf]
  11. Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
    Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:152-159 [Conf]
  12. Tsung-Chuan Huang, Slo-Li Chu
    SAGE: A New Analysis and Optimization System for FlexRAM Architecture. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:160-168 [Conf]
  13. Koji Inoue, Koji Kai, Kazuaki Murakami
    Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:169-178 [Conf]
  14. Jeff La Coss
    The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:179-182 [Conf]
  15. Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta
    Compiler-Directed Cache Line Size Adaptivity. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:183-187 [Conf]

  16. Workshop Notes. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:188-192 [Conf]
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