Conferences in DBLP

International Conference on Parallel Architectures and Compilation Techniques (PACT) (IEEEpact)
2000 (conf/IEEEpact/2000)

1. Mikhail Smelyanskiy, Gary S. Tyson, Edward S. Davidson
   Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2000, pp:3-12 [Conf]
   
2. Jason Hiser, Steve Carr, Philip H. Sweany
   Global Register Partitioning. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2000, pp:13-23 [Conf]
   
3. Tom Way, Ben Breech, Lori L. Pollock
   Region Formation Analysis with Demand-Driven Inlining for Region-Based Optimization. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2000, pp:24-36 [Conf]
   
4. Jian Liang, Sriram Swaminathan, Russell Tessier
   aSOC: A Scalable, Single-Chip Communications Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2000, pp:37-46 [Conf]
   
5. Ilanthiraiyan Pragaspathy, Babak Falsafi
   Address Partitioning in DSM Clusters with Parallel Coherence Controllers. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2000, pp:47-56 [Conf]
   
6. Bruce R. Childers, Jack W. Davidson
   Custom Wide Counterflow Pipelines for High-Performance Embedded Applications. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2000, pp:57-70 [Conf]
   
7. Kim M. Hazelwood, Thomas M. Conte
   A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2000, pp:71-80 [Conf]
   
8. Kevin Scott, Jack W. Davidson
   Exploring the Limits of Sub-Word Level Parallelism. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2000, pp:81-91 [Conf]
   
9. Amarildo T. da Costa, Felipe M. G. França, Eliseu M. Chaves Filho
   The Dynamic Trace Memorization Reuse Technique. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2000, pp:92-99 [Conf]
   
10. Jian Huang, David J. Lilja
    Exploring Sub-Block Value Reuse for Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:100-110 [Conf]
    
11. Jaejin Lee, David A. Padua
    Hiding Relaxed Memory Consistency with Compilers. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:111-122 [Conf]
    
12. David M. Koppelman
    Neighborhood Prefetching on Multiprocessors Using Instruction History. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:123-132 [Conf]
    
13. Gordon B. Bell, Kevin M. Lepak, Mikko H. Lipasti
    Characterization of Silent Stores. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:133-144 [Conf]
    
14. Sang Jeong Lee, Pen-Chung Yew
    On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:145-156 [Conf]
    
15. Roy Dz-Ching Ju, Kevin Nomura, Uma Mahadevan, Le-Chun Wu
    A Unified Compiler Framework for Control and Data Speculation. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:157-168 [Conf]
    
16. Uma Mahadevan, Kevin Nomura, Roy Dz-Ching Ju, Rick Hank
    Applying Data Speculation in Modulo Scheduled Loops. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:169-178 [Conf]
    
17. Jayanth Gummaraju, Manoj Franklin
    Branch Prediction in Multi-Threaded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:179-188 [Conf]
    
18. Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    The Effect of Code Reordering on Branch Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:189-198 [Conf]
    
19. Kevin Skadron, Margaret Martonosi, Douglas W. Clark
    A Taxonomy of Branch Mispredictions, and Alloyed Prediction as a Robust Solution to Wrong-History Mispredictions. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:199-206 [Conf]
    
20. Jan Hoogerbrugge
    Dynamic Branch Prediction for a VLIW Processor. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:207-216 [Conf]
    
21. Luís M. B. Lopes, Fernando M. A. Silva, Vasco Thudichum Vasconcelos
    Fine Grained Multithreading with Process Calculi. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:217-226 [Conf]
    
22. Mahmut T. Kandemir, J. Ramanujam
    Data Relation Vectors: A New Abstraction for Data Optimizations. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:227-236 [Conf]
    
23. Toru Kisuki, Peter M. W. Knijnenburg, Michael F. P. O'Boyle
    Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:237-248 [Conf]
    
24. Kang Su Gatlin, Larry Carter
    Faster FFTs via Architecture-Cognizance. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:249-260 [Conf]
    
25. Edwin Naroska, Rung-Ji Shang, Feipei Lai, Uwe Schwiegelshohn
    Hybrid Parallel Circuit Simulation Approaches. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:261-270 [Conf]
    
26. Martin Schulz
    Multithreaded Programming of PC Clusters. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:271-280 [Conf]
    
27. Hui Wu, Joxan Jaffar, Roland H. C. Yap
    A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:281-290 [Conf]
    
28. Rainer Leupers
    Instruction Scheduling for Clustered VLIW DSPs. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:291-300 [Conf]
    
29. Santosh G. Abraham, Waleed Meleis, Ivan D. Baev
    Efficient Backtracking Instruction Schedulers. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:301-308 [Conf]