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Conferences in DBLP

International On-Line Testing Symposium / Workshop (iolts)
2004 (conf/iolts/2004)

  1. V. Agarwal
    A Pragmatic Approach to On-Line Testing. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:1-4 [Conf]
  2. Daniel Barros Jr., Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Modeling and Simulation of Time Domain Faults in Digital Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:5-10 [Conf]
  3. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
    Sizing CMOS Circuits for Increased Transient Error Tolerance. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:11-16 [Conf]
  4. José Manuel Cazeaux, Martin Omaña, Cecilia Metra
    Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:17-24 [Conf]
  5. V. Saposhnikov, Vl. V. Saposhnikov, A. Morozov, Michael Gössel
    Necessary and Sufficient Conditions for the Existence of Totally Self-Checking Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:25-30 [Conf]
  6. Vitalij Ocheretnij, Daniel Marienfeld, Egor S. Sogomonyan, Michael Gössel
    Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:31-36 [Conf]
  7. Claudia Kretzschmar, Christian Galke, Heinrich Theodor Vierhaus
    A Hierarchical Self Test Scheme for SoCs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:37-44 [Conf]
  8. Steffen Tarnick
    Single-Output Embedded Checkers for Systematic Unordered Codes. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:45-51 [Conf]
  9. A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky
    A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:52-57 [Conf]
  10. José Manuel Cazeaux, Daniele Rossi, Cecilia Metra
    New High Speed CMOS Self-Checking Voter. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:58-66 [Conf]
  11. Andrzej Krasniewski
    Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:67-72 [Conf]
  12. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Low Cost On-Line Testing of RF Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:73-78 [Conf]
  13. Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante
    Hybrid Soft Error Detection by Means of Infrastructure IP Cores. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:79-88 [Conf]
  14. P. D. Hyde, G. Russell
    A Comparative Study of the Design of Synchronous and Asynchronous Self-Checking RISC Processors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:89-94 [Conf]
  15. Eric F. Weglarz, Kewal K. Saluja, T. M. Mak
    Testing of Hard Faults in Simultaneous Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:95-100 [Conf]
  16. Hamid R. Zarandi, Seyed Ghassem Miremadi, Hamid Sarbazi-Azad
    Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:101-108 [Conf]
  17. Mario García-Valderas, Celia López-Ongil, Marta Portela-García, Luis Entrena
    Transient Fault Emulation of Hardened Circuits in FPGA Platforms. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:109-114 [Conf]
  18. Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
    On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:115-120 [Conf]
  19. Yannick Monnet, Marc Renaudin, Régis Leveugle
    Asynchronous Circuits Sensitivity to Fault Injection. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:121-128 [Conf]
  20. Amine M'sir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley
    Designing a High Speed Decoder for Cyclic Codes. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:129-134 [Conf]
  21. Daniele Rossi, A. Muccio, André K. Nieuwland, Atul Katoch, Cecilia Metra
    Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:135-140 [Conf]
  22. Gian-Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
    A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:141-148 [Conf]
  23. Amit Agarwal, Bipul Chandra Paul, Kaushik Roy
    A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:149-154 [Conf]
  24. Miguel Garvie, Adrian Thompson
    Scrubbing Away Transients and Jiggling Around the Permanent: Long Survival of FPGA Systems Through Evolutionary Self-Repair. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:155-160 [Conf]
  25. Cecilia Metra, A. Ferrari, Martin Omaña, Andrea Pagni
    Hardware Reconfiguration Scheme for High Availability Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:161-166 [Conf]
  26. Michele Portolan, Régis Leveugle
    Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:167-174 [Conf]
  27. Eberhard Böhl, Elmar Dilger, M. Böhl
    A New Code with Reduced EMI and Partial EC Possibilities. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:175- [Conf]
  28. Thomas O'Shea, Ian A. Grout
    A Matlab Based On-Chip Signal Generation and Analysis Environment for Mixed Signal Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:176- [Conf]
  29. André K. Nieuwland, Patrick Gindner
    Automated Logic SER Analysis and On-Line SER reduction. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:177- [Conf]
  30. Jose Miguel Vieira dos Santos
    On the Design of Long-Life Reliable Systems for Ground-Based Applications. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:178- [Conf]
  31. Rodrigo Picos, Miquel Roca, Eugeni Isern, Sebstatià A. Bota, Eugenio García
    On-line Monitoring Capabilities of Oscillation Test Techniques: Results Demonstration in an OTA. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:179- [Conf]
  32. Carlos Arthur Lang Lisbôa, Luigi Carro
    An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:180- [Conf]
  33. Petr Fiser, Hana Kubatova
    Survey of the Algorithms in the Column-Matching BIST Method. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:181- [Conf]
  34. Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
    A Technique to Reduce Power and Test Application Time in BIST. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:182-183 [Conf]
  35. Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra
    Optimization of the Theory of FDD of DES for Alleviation of the State Explosion Problem and Development of CAD Tools for On-line Testing of Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:184-0 [Conf]
  36. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
    BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:187-192 [Conf]
  37. P. Karpodinis, Dimitri Kagaris, Dimitris Nikolos
    Accumulator based Test-per-Scan BIST. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:193-198 [Conf]
  38. B. Alorda, V. Canals, I. de Paúl, Jaume Segura
    A BIST-based Charge Analysis for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:199-206 [Conf]
  39. Nikolaos G. Bartzoudis, Alexandros G. Fragkiadakis, David J. Parish, Jose Luis Nunez
    A System for Fault Detection and Reconfiguration of Hardware Based Active Networks. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:207-213 [Conf]
  40. Elmar Dilger, Roland Karrelmeyer, Bernd Straube
    Fault Tolerant Mechatronics. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:214-218 [Conf]
  41. David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell
    Scan Design and Secure Chip. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:219-226 [Conf]
  42. Abdelaziz Ammari, K. Hadjiat, Régis Leveugle
    On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:227-232 [Conf]
  43. B. Nicolescu, Yvon Savaria, Raoul Velazco
    Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:233-238 [Conf]
  44. Amir Rajabzadeh, Seyed Ghassem Miremadi, Mirzad Mohandespour
    Experimental Evaluation of Master/Checker Architecture Using Power Supply- and Software-Based Fault Injection. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:239-246 [Conf]
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