Conferences in DBLP
V. Agarwal A Pragmatic Approach to On-Line Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Barros Jr. , Fabian Vargas , Marcelino B. Santos , Isabel C. Teixeira , João Paulo Teixeira Modeling and Simulation of Time Domain Faults in Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yuvraj Singh Dhillon , Abdulkadir Utku Diril , Abhijit Chatterjee , Adit D. Singh Sizing CMOS Circuits for Increased Transient Error Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] José Manuel Cazeaux , Martin Omaña , Cecilia Metra Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop. [Citation Graph (0, 0)][DBLP ] Conf ] V. Saposhnikov , Vl. V. Saposhnikov , A. Morozov , Michael Gössel Necessary and Sufficient Conditions for the Existence of Totally Self-Checking Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Vitalij Ocheretnij , Daniel Marienfeld , Egor S. Sogomonyan , Michael Gössel Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Claudia Kretzschmar , Christian Galke , Heinrich Theodor Vierhaus A Hierarchical Self Test Scheme for SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Steffen Tarnick Single-Output Embedded Checkers for Systematic Unordered Codes. [Citation Graph (0, 0)][DBLP ] Conf ] A. Rao , Th. Haniotakis , Y. Tsiatouhas , V. Kaky A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] José Manuel Cazeaux , Daniele Rossi , Cecilia Metra New High Speed CMOS Self-Checking Voter. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelo Negreiros , Luigi Carro , Altamiro Amadeu Susin Low Cost On-Line Testing of RF Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Leticia Maria Veiras Bolzani , Maurizio Rebaudengo , Matteo Sonza Reorda , Fabian Vargas , Massimo Violante Hybrid Soft Error Detection by Means of Infrastructure IP Cores. [Citation Graph (0, 0)][DBLP ] Conf ] P. D. Hyde , G. Russell A Comparative Study of the Design of Synchronous and Asynchronous Self-Checking RISC Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Eric F. Weglarz , Kewal K. Saluja , T. M. Mak Testing of Hard Faults in Simultaneous Multithreaded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Hamid R. Zarandi , Seyed Ghassem Miremadi , Hamid Sarbazi-Azad Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Mario García-Valderas , Celia López-Ongil , Marta Portela-García , Luis Entrena Transient Fault Emulation of Hardened Circuits in FPGA Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Bernardi , Matteo Sonza Reorda , Luca Sterpone , Massimo Violante On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Yannick Monnet , Marc Renaudin , Régis Leveugle Asynchronous Circuits Sensitivity to Fault Injection. [Citation Graph (0, 0)][DBLP ] Conf ] Amine M'sir , Fabrice Monteiro , Abbas Dandache , Bernard Lepley Designing a High Speed Decoder for Cyclic Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Daniele Rossi , A. Muccio , André K. Nieuwland , Atul Katoch , Cecilia Metra Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Gian-Carlo Cardarilli , Marco Ottavi , Salvatore Pontarelli , Marco Re , Adelio Salsano A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Agarwal , Bipul Chandra Paul , Kaushik Roy A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Miguel Garvie , Adrian Thompson Scrubbing Away Transients and Jiggling Around the Permanent: Long Survival of FPGA Systems Through Evolutionary Self-Repair. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , A. Ferrari , Martin Omaña , Andrea Pagni Hardware Reconfiguration Scheme for High Availability Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Michele Portolan , Régis Leveugle Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Eberhard Böhl , Elmar Dilger , M. Böhl A New Code with Reduced EMI and Partial EC Possibilities. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas O'Shea , Ian A. Grout A Matlab Based On-Chip Signal Generation and Analysis Environment for Mixed Signal Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] André K. Nieuwland , Patrick Gindner Automated Logic SER Analysis and On-Line SER reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Jose Miguel Vieira dos Santos On the Design of Long-Life Reliable Systems for Ground-Based Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Rodrigo Picos , Miquel Roca , Eugeni Isern , Sebstatià A. Bota , Eugenio García On-line Monitoring Capabilities of Oscillation Test Techniques: Results Demonstration in an OTA. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Arthur Lang Lisbôa , Luigi Carro An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets. [Citation Graph (0, 0)][DBLP ] Conf ] Petr Fiser , Hana Kubatova Survey of the Algorithms in the Column-Matching BIST Method. [Citation Graph (0, 0)][DBLP ] Conf ] Debjyoti Ghosh , Swarup Bhunia , Kaushik Roy A Technique to Reduce Power and Test Application Time in BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Santosh Biswas , Siddhartha Mukhopadhyay , Amit Patra Optimization of the Theory of FDD of DES for Alleviation of the State Explosion Problem and Development of CAD Tools for On-line Testing of Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Olivier Héron , Serge Pravossoudovitch , Michel Renovell BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] P. Karpodinis , Dimitri Kagaris , Dimitris Nikolos Accumulator based Test-per-Scan BIST. [Citation Graph (0, 0)][DBLP ] Conf ] B. Alorda , V. Canals , I. de Paúl , Jaume Segura A BIST-based Charge Analysis for Embedded Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaos G. Bartzoudis , Alexandros G. Fragkiadakis , David J. Parish , Jose Luis Nunez A System for Fault Detection and Reconfiguration of Hardware Based Active Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Elmar Dilger , Roland Karrelmeyer , Bernd Straube Fault Tolerant Mechatronics. [Citation Graph (0, 0)][DBLP ] Conf ] David Hély , Marie-Lise Flottes , Frédéric Bancel , Bruno Rouzeyre , Nicolas Bérard , Michel Renovell Scan Design and Secure Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Abdelaziz Ammari , K. Hadjiat , Régis Leveugle On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] B. Nicolescu , Yvon Savaria , Raoul Velazco Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Amir Rajabzadeh , Seyed Ghassem Miremadi , Mirzad Mohandespour Experimental Evaluation of Master/Checker Architecture Using Power Supply- and Software-Based Fault Injection. [Citation Graph (0, 0)][DBLP ] Conf ] 