Conferences in DBLP

International Conference on Parallel Architectures and Compilation Techniques (PACT) (IEEEpact)
2004 (conf/IEEEpact/2004)

1. Cédric Bastoul
   Code Generation in the Polyhedral Model Is Easier Than You Think. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2004, pp:7-16 [Conf]
   
2. Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai
   A Compiler Framework for Recovery Code Generation in General Speculative Optimizations. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2004, pp:17-28 [Conf]
   
3. Yuri Dotsenko, Cristian Coarfa, John M. Mellor-Crummey
   A Multi-Platform Co-Array Fortran Compiler. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2004, pp:29-40 [Conf]
   
4. M. Anton Ertl, David Gregg
   Retargeting JIT Compilers by using C-Compiler Generated Executable Code. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2004, pp:41-50 [Conf]
   
5. Marc Epalza, Paolo Ienne, Daniel Mlynek
   Adding Limited Reconfigurability to Superscalar Processors. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2004, pp:53-62 [Conf]
   
6. Alex Settle, Joshua L. Kihm, Andrew Janiszewski, Daniel A. Connors
   Architectural Support for Enhanced SMT Job Scheduling. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2004, pp:63-73 [Conf]
   
7. Ramadass Nagarajan, Sundeep K. Kushwaha, Doug Burger, Kathryn S. McKinley, Calvin Lin, Stephen W. Keckler
   Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2004, pp:74-84 [Conf]
   
8. Leonardo R. Bachega, Siddhartha Chatterjee, Kenneth A. Dockser, John A. Gunnels, Manish Gupta, Fred G. Gustavson, Christopher A. Lapkowski, Gary K. Liu, Mark P. Mendell, Charles D. Wait, T. J. Christopher Ward
   A High-Performance SIMD Floating Point Unit for BlueGene/L: Architecture, Compilation, and Algorithm Design. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2004, pp:85-96 [Conf]
   
9. Tulika Mitra, Abhik Roychoudhury, Qinghua Shen
   Impact of Java Memory Model on Out-of-Order Multiprocessors. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2004, pp:99-110 [Conf]
   
10. Seongbeom Kim, Dhruba Chandra, Yan Solihin
    Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:111-122 [Conf]
    
11. Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Chenghuai Lu
    Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:123-134 [Conf]
    
12. Kyle J. Nesbit, Ashutosh S. Dhodapkar, James E. Smith
    AC/DC: An Adaptive Data Cache Prefetcher. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:135-145 [Conf]
    
13. Tadashi Watanabe
    The Earth Simulator and Beyond-Technological Considerations Toward the Sustained PetaFlops Machine. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:149-0 [Conf]
    
14. YongKang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, David H. Albonesi
    The Energy Impact of Aggressive Loop Fusion. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:153-164 [Conf]
    
15. Dhruva R. Chakrabarti, Luis A. Lozano, Xinliang D. Li, Robert Hundt, Shin-Ming Liu
    Scalable High Performance Cross-Module Inlining. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:165-176 [Conf]
    
16. Ram Rangan, Neil Vachharajani, Manish Vachharajani, David I. August
    Decoupled Software Pipelining with the Synchronization Array. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:177-188 [Conf]
    
17. Wen Xu, Sanjeev Kumar, Kai Li
    Fast Paths in Concurrent Programs. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:189-200 [Conf]
    
18. Jialin Dou, Marcelo H. Cintra
    Compiler Estimation of Load Imbalance Overhead in Speculative Parallelization. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:203-214 [Conf]
    
19. Gladys Utrera, Julita Corbalán, Jesús Labarta
    Implementing Malleability on MPI Jobs. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:215-224 [Conf]
    
20. Michael Ball, Cristina Cifuentes, Deepankar Bairagi
    Partitioning of Code for a Massively Parallel Machine. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:225-236 [Conf]
    
21. Stamatis Vassiliadis
    Polymorphic Processors: How to Expose Arbitrary Hardware Functionality to Programmers. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:239-0 [Conf]
    
22. Silvius Rus, Dongmin Zhang, Lawrence Rauchwerger
    The Value Evolution Graph and its Use in Memory Reference Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:243-254 [Conf]
    
23. Takeshi Ogasawara, Hideaki Komatsu, Toshio Nakatani
    TO-Lock: Removing Lock Overhead Using the Owners' Temporal Locality. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:255-266 [Conf]
    
24. Francois Labonte, Peter R. Mattson, William Thies, Ian Buck, Christos Kozyrakis, Mark Horowitz
    The Stream Virtual Machine. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:267-277 [Conf]
    
25. Hao Yu, Dongmin Zhang, Lawrence Rauchwerger
    An Adaptive Algorithm Selection Framework. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:278-289 [Conf]