Conferences in DBLP
Keith Whisnant , Zbigniew Kalbarczyk , Ravishankar K. Iyer Micro-Checkpointing: Checkpointing for Multithreaded Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Benso , Silvia Chiusano , Paolo Prinetto A COTS Wrapping Toolkit for Fault Tolerant Applications under Windows NT. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Rebaudengo , Matteo Sonza Reorda , Massimo Violante , Ph. Cheynet , B. Nicolescu , Raoul Velazco Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Lukás Sekanina , Vladimír Drábek Relation between Fault Tolerance and Reconfiguration in Cellular Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , Charles E. Stroud , Brandon Skaggs , John M. Emmert Improving On-Line BIST-Based Diagnosis for Roving STARs. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski Self-Testing of FPGA Delay Faults in the System Environment. [Citation Graph (0, 0)][DBLP ] Conf ] J. A. Sainz , R. Muñoz , J. A. Maiz , L. A. Aguado , Miquel Roca A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] V. Pouget , P. Fouillat , D. Lewis , H. Lapuyade , L. Sarger , F. M. Roche , S. Duzellier , R. Ecoffet An Overview of the Applications of a Pulsed Laser System for SEU Testing. [Citation Graph (0, 0)][DBLP ] Conf ] B. Parrotta , Maurizio Rebaudengo , Matteo Sonza Reorda , Massimo Violante New Techniques for Accelerating Fault Injection in VHDL Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Fabian Vargas , Alexandre M. Amory , Raoul Velazco Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Gil , J. Gracia , J. C. Baraza , Pedro J. Gil A Study of the Effects of Transient Fault Injection into the VHDL Model of a Fault-Tolerant Microcomputer System. [Citation Graph (0, 0)][DBLP ] Conf ] Raoul Velazco , S. Rezgui Transient Bitflip Injection in Microprocessor Embedded Applications. [Citation Graph (0, 0)][DBLP ] Conf ] B. Alorda , I. de Paúl , Jaume Segura , T. Miller On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Margala , Srdjan Dragic , Ahmed El-Abasiry , Samuel Ekpe , Viera Stopjaková I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog Test. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Tsiatouhas , Th. Haniotakis , Dimitris Nikolos A Compact Built-In Current Sensor for IDDQ Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Maidon , Yann Deval , Jean-Baptiste Begueret An Improved CMOS BICS for On-Line Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Jose Miguel Vieira dos Santos Concurrent Scan Monitoring and Multi-Pattern Search. [Citation Graph (0, 0)][DBLP ] Conf ] Ahmad Abdelhay , Emmanuel Simeu Analytical Redundancy Based Approach for Concurrent Fault Detection in Linear Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Christian Landrault , Serge Pravossoudovitch , Arnaud Virazel Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Ondrej Novák , Jiri Nosek On Using Deterministic Test Sets in BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaodong Zhang , Kaushik Roy Power Reduction in Test-Per-Scan BIST. [Citation Graph (0, 0)][DBLP ] Conf ] A. Morozov , V. V. Saposhnikov , Vl. V. Saposhnikov , Michael Gössel New Self-Checking Circuits by Use of Berger-Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Gössel , Alexej Dmitriev , Vl. V. Saposhnikov , V. V. Saposhnikov A New Method for Concurrent Checking by Use of a 1-out-of-4 Code. [Citation Graph (0, 0)][DBLP ] Conf ] A. Matrosova , Sergey Ostanin Self-Checking FSM Design with Observing only FSM Outputs. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Migliavacca Faster Time-to-Market, Lower Cost of Development and Test for Standard Analog IC. [Citation Graph (0, 0)][DBLP ] Conf ] K. D. R. Jagath-Kumara Theoretical Performance Bounds of a Probability of Bit Error Estimator Used in Digital Links Employing Binary Block Codes. [Citation Graph (0, 0)][DBLP ] Conf ] T. Vallino , Abbas Dandache , J. P. Delahaye , Fabrice Monteiro , Bernard Lepley A Stamping Technique to Increase the Error Correction Capacity of the (127, k, d) RS Code. [Citation Graph (0, 0)][DBLP ] Conf ] Debaleena Das , Nur A. Touba , Markus Seuring , Michael Gössel Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes. [Citation Graph (0, 0)][DBLP ] Conf ] M. E. Nillesen , A. Del Pizzo , M. Pasquariello , R. Rizzo A Very Flexible DSP-Based Controller for On-Line Test and Control of Industrial Processes. [Citation Graph (0, 0)][DBLP ] Conf ] Naotake Kamiura , Masashi Tomita , Teijiro Isokawa , Nobuyuki Matsui On Realization of Fault-Tolerant Fuzzy Controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis , N. Zaidan , Th. Calin , D. Bied-Charreton ISIS: A Fail-Safe Interface Realized in Smart Power Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad A. Naal , Emmanuel Simeu High-Level Synthesis Methodology for On-Line Testability Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Sosnowski Improving Fault Coverage in System Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Benso , Silvia Chiusano , Giorgio Di Natale , Paolo Prinetto , Monica Lobetti Bodoni A Family of Self-Repair SRAM Cores. [Citation Graph (0, 0)][DBLP ] Conf ] 