Conferences in DBLP
Alfredo Benso , Stefano Di Carlo , Giorgio Di Natale , Luca Tagliaferri , Paolo Prinetto Validation of a Software Dependability Tool via Fault Injection Experiments. [Citation Graph (0, 0)][DBLP ] Conf ] Pierluigi Civera , Luca Macchiarulo , Maurizio Rebaudengo , Matteo Sonza Reorda , Massimo Violante Exploiting FPGA for Accelerating Fault Injection Experiments. [Citation Graph (0, 0)][DBLP ] Conf ] Joakim Aidemark , Peter Folkesson , Johan Karlsson Path-Based Error Coverage Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Piotr Gawkowski , Janusz Sosnowski Analyzing Fault Effects in Fault Insertion Experiments. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , Charles E. Stroud , Matthew Lashinsky , Jeremy Nall , John M. Emmert On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel G. Gericota , Gustavo R. Alves , Miguel L. Silva , José M. Ferreira DRAFT: An On-Line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Luis Entrena , Celia López , Emilio Olías , Enrique San Millán , José Alberto Espejo Logic Optimization of Unidirectional Circuits with Structural Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Luis Entrena , Celia López , Emilio Olías Automatic Insertion of Fault-Tolerant Structures at the RT Level. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Pflanz , K. Walther , Heinrich Theodor Vierhaus On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity. [Citation Graph (0, 0)][DBLP ] Conf ] Monica Alderighi , Sergio D'Angelo , Giacomo R. Sechi , Cecilia Metra Novel Fault-Tolerant Adder Design for FPGA-Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dhiraj K. Pradhan Logic Insertion to Speed-Up Logic Verification: A Recent Development. [Citation Graph (0, 0)][DBLP ] Conf ] Mrinal Bose , Elizabeth M. Rudnick , Magdy S. Abadir Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitri Kagaris , Spyros Tragoudas Using a WLFSR to Embed Test Pattern Pairs in Minimum Time. [Citation Graph (0, 0)][DBLP ] Conf ] Emmanouil Kalligeros , Xrysovalantis Kavousianos , Dimitris Bakalis , Dimitris Nikolos A New Reseeding Technique for LFSR-Based Test Pattern Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Yannick Bonhomme , Patrick Girard , Loïs Guiller , Christian Landrault , Serge Pravossoudovitch A Gated Clock Scheme for Low Power Scan-Based BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Ondrej Novák , Jiri Nosek Test-per-Clock Testing of the Circuits with Scan. [Citation Graph (0, 0)][DBLP ] Conf ] Octavian Petre , Hans G. Kerkhoff Increasing the Fault Coverage in Multiple Clock Domain Systems by Using On-Line Testing of Synchronizers. [Citation Graph (0, 0)][DBLP ] Conf ] Michele Favalli , Cecilia Metra Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Tsiatouhas , Th. Haniotakis , Dimitris Nikolos , Costas Efstathiou Concurrent Detection of Soft Errors Based on Current Monitoring. [Citation Graph (0, 0)][DBLP ] Conf ] D. Lewis , H. Lapuyade , Yann Deval , Y. Maidon , F. Darracq , R. Briand , P. Fouillat A New Laser System for X-Rays Flashes Sensitivity Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Manzone , Alessandro Pincetti , Diego De Costantini Fault Tolerant Automotive Systems: An Overview. [Citation Graph (0, 0)][DBLP ] Conf ] José Luis Merino , Sebastià A. Bota , A. Herms , Josep Samitier , Enric Cabruja , X. Jordà , M. Vellvehí , J. Bausells , A. Ferré , J. Bigorr Smart Temperature Sensor for On-Line Monitoring in Automotive Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ashish Syal , Victor Lee , André Ivanov , Josep Altet CMOS Differential and Absolute Thermal Sensors. [Citation Graph (0, 0)][DBLP ] Conf ] Parag K. Lala , Mark G. Karpovsky An Approach for Designing On-Line Testable State Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaodong Zhang , Kaushik Roy Power Constrained Test Scheduling with Low Power Weighted Random Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiana Bolchini , Fabio Salice , Donatella Sciuto Designing Reliable Embedded Systems Based on 32 Bit Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Chouki Aktouf On-Line Testing in Continuous Operation of Embedded Systems: Modeling and Performance Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Böhnel , Reinhold Weiss Self-Stabilization Testing of LUT-Based FPGA Designs by Fault Injection. [Citation Graph (0, 0)][DBLP ] Conf ] J. Gracia , J. C. Baraza , Daniel Gil , Pedro J. Gil A Study of the Experimental Validation of Fault-Tolerant Systems Using Different VHDL-Based Fault Injection Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Jose Miguel Vieira dos Santos TRACS-TRansient Activity Checking with Scan Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Zan Yang , Gwan Choi An On-Line Testing Approach Using Code-Perturbation. [Citation Graph (0, 0)][DBLP ] Conf ] Richard P. Kleihorst , Nico Benschop Fault Tolerant ICs by Area-Optimized Error Correcting Codes. [Citation Graph (0, 0)][DBLP ] Conf ] A. Matrosova , K. Nikitin , O. Goloubeva Totally Self-Checking FSM Design Based on Multilevel Synthesis Methods and FPGA Implemetation. [Citation Graph (0, 0)][DBLP ] Conf ] Vitalij Ocheretnij , Michael Gössel , Egor S. Sogomonyan Code-Disjoint Carry-Dependent Sum Adder with Partial Look-Ahead. [Citation Graph (0, 0)][DBLP ] Conf ] Stanislaw J. Piestrak , Dimitris Bakalis , Xrysovalantis Kavousianos On the Design of Self-Testing Checkers for Modified Berger Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Fabrice Monteiro , Abbas Dandache , Bernard Lepley Fast Configurable Polynomial Division for Error Control Coding Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiana Bolchini , Luigi Pomante , Fabio Salice , Donatella Sciuto Reliability Properties Assessment at System Level: A Co-design Framework. [Citation Graph (0, 0)][DBLP ] Conf ] B. Nicolescu , Raoul Velazco , Matteo Sonza Reorda Effectiveness and Limitations of Various Software Techniques for "Soft Error" Detection: A Comparative Study. [Citation Graph (0, 0)][DBLP ] Conf ] Isabel González , Luis Berrojo Supporting Fault Tolerance in an Industrial Environment: The AMATISTA Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Fabian Vargas , Rubem Dutra R. Fagundes , Daniel Barros Jr. A New Approach to Design Reliable Real-Time Speech Recognition Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Gaetano Palumbo , Giuseppe Introvaia , Vincenzo Mastrocola , Promod Kumar , Francesco Pipiton Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando M. Gonçalves , Marcelino B. Santos , Isabel C. Teixeira , João Paulo Teixeira Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. [Citation Graph (0, 0)][DBLP ] Conf ] Naotake Kamiura , Teijiro Isokawa , Nobuyuki Matsui , Kazuharu Yamato On-Line Multiple-Fault-Detection of Fuzzy Controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Emmanuel Simeu , Ahmad Abdelhay A Robust Fault Detection Scheme for Concurrent Testing of Linear Digital Systems. [Citation Graph (0, 0)][DBLP ] Conf ] M. Artioli , F. Filippetti Fault Diagnosis for Linear Analog Circuits with Symbolic Analysis and Reduced Observable Point Set. [Citation Graph (0, 0)][DBLP ] Conf ] Cristoforo Marzocca , Francesco Corsi Mixed-Signal Circuit Classification in a Pseudorandom Testing Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] 