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Conferences in DBLP

International On-Line Testing Symposium / Workshop (iolts)
2005 (conf/iolts/2005)


  1. Program Committee. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:- [Conf]

  2. Organizing Committee. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:- [Conf]

  3. IEEE Computer Society TTTC: Test Technology Technical Council. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:- [Conf]

  4. Welcome. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:- [Conf]
  5. Tino Heijmen
    Analytical Semi-Empirical Model for SER Sensitivity Estimation of Deep-Submicron CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:3-8 [Conf]
  6. A. Douin, V. Pouget, D. Lewis, P. Fouillat, Philippe Perdu
    Electrical Modeling for Laser Testing with Different Pulse Durations. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:9-13 [Conf]
  7. Piotr Gawkowski, Janusz Sosnowski, B. Radko
    Analyzing the Effectiveness of Fault Hardening Procedures. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:14-19 [Conf]
  8. José Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee
    On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:23-28 [Conf]
  9. Cristiano Lazzari, Lorena Anghel, Ricardo A. L. Reis
    On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:29-34 [Conf]
  10. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra
    Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:35-40 [Conf]
  11. Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes
    Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:43-48 [Conf]
  12. Monica Alderighi, A. Candelori, Fabio Casini, Sergio D'Angelo, M. Mancini, A. Paccagnella, S. Pastore, Giacomo R. Sechi
    Heavy Ion Effects on Configuration Logic of Virtex FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:49-53 [Conf]
  13. Matteo Sonza Reorda, Luca Sterpone, Massimo Violante
    Efficient Estimation of SEU Effects in SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:54-59 [Conf]
  14. Yervant Zorian, Valery A. Vardanian, K. Aleksanyan, K. Amirkhanyan
    Impact of Soft Error Challenge on SoC Design. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:63-68 [Conf]
  15. T. M. Mak, Subhasish Mitra, Ming Zhang
    DFT Assisted Built-In Soft Error Resilience. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:69- [Conf]
  16. Robert Aitken, Betina Hold
    Modeling Soft-Error Susceptibility for IP Blocks. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:70-73 [Conf]
  17. Ishwar Parulkar, Robert Cypher
    Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:74-77 [Conf]
  18. Lorena Anghel, Michael Nicolaidis
    Simulation and Mitigation of Single Event Effects. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:81- [Conf]
  19. Frederic Wrobel
    Use of Nuclear Codes for Neutron-Induced Nuclear Reactions in Microelectronics. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:82-86 [Conf]
  20. G. Hubert, N. Buard, C. Weulersse, T. Carriere, M.-C. Palau, J.-M. Palau, D. Lambert, J. Baggio, F. Wrobel, F. Saigne, R. Gaillard
    A Review of DASIE Code Family: Contribution to SEU/MBU Understanding. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:87-94 [Conf]
  21. Michael Nicolaidis
    Design for Mitigation of Single Event Effects. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:95-96 [Conf]
  22. T. M. Mak
    Does It Mean Less Testing for Self Calibrating Design?. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:99- [Conf]
  23. Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy
    Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:100-105 [Conf]
  24. Donghoon Han, Selim Sermet Akbay, Soumendu Bhattacharya, Abhijit Chatterjee, William R. Eisenstadt
    On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST). [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:106-111 [Conf]
  25. Régis Leveugle
    Introduction to the Special Session on Secure Implementations. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:115- [Conf]
  26. Antoine Lemarechal
    Introduction to Fault Attacks on Smartcard. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:116- [Conf]
  27. Laurent Sourgen
    Security Constraints in Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:117- [Conf]
  28. Lejla Batina, Nele Mentens, Ingrid Verbauwhede
    Side-Channel Issues for Designing Secure Hardware Implementations. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:118-121 [Conf]
  29. Alain Merle, Jessy Clédière
    Security Testing for Hardware Products: The Security Evaluations Practice. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:122-125 [Conf]
  30. Yannick Monnet, Marc Renaudin, Régis Leveugle
    Hardening Techniques against Transient Faults for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:129-134 [Conf]
  31. Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev, Deepali Koppad
    On-Line Testing of Globally Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:135-140 [Conf]
  32. Vitalij Ocheretnij, G. Kouznetsov, Ramesh Karri, Michael Gössel
    On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box Implementations. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:141-146 [Conf]
  33. S. Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou
    Fast, Parallel Two-Rail Code Checker with Enhanced Testability. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:149-156 [Conf]
  34. Julian Murphy, Alexandre V. Bystrov, Alexandre Yakovlev
    Power-Balanced Self Checking Circuits for Cryptographic Chips. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:157-162 [Conf]
  35. Martin Omaña, O. Losco, Cecilia Metra, Andrea Pagni
    On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:163-168 [Conf]
  36. Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy
    Process Variation Tolerant Online Current Monitor for Robust Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:171-176 [Conf]
  37. B. Alorda, Sebastià A. Bota, Jaume Segura
    A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:177-182 [Conf]
  38. André K. Nieuwland, Atul Katoch, Daniele Rossi, Cecilia Metra
    Coding Techniques for Low Switching Noise in Fault Tolerant Busses. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:183-189 [Conf]
  39. Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache
    Modeling of Transients Caused by a Laser Attack on Smart Cards. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:193-194 [Conf]
  40. Riccardo Mariani, Gabriele Boschi
    Scrubbing and Partitioning for Protection of Memory Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:195-196 [Conf]
  41. Andrzej Krasniewski
    A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:197-198 [Conf]
  42. Amandeep Singh, Debashish Bose
    A Software Based Online Memory Test for Highly Available Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:199-200 [Conf]
  43. Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
    Design of a Self Checking Reed Solomon Encoder. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:201-202 [Conf]
  44. Kentaroh Katoh, Abderrahim Doumar, Hideo Ito
    Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:203-204 [Conf]
  45. Amir Rajabzadeh
    A 32-Bit COTS-Based Fault-Tolerant Embedded System. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:205-206 [Conf]
  46. Fabian Vargas, D. L. Cavalcante, E. Gatti, Dárcio Prestes, D. Lupi
    On the Proposition of an EMI-Based Fault Injection Approach. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:207-208 [Conf]
  47. Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert
    On-Line Testing for Secure Implementations: Design and Validation. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:211- [Conf]
  48. Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis
    Accumulator-Based Weighted Pattern Generation. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:215-220 [Conf]
  49. Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir
    A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:221-226 [Conf]
  50. George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
    Test Generation Methodology for High-Speed Floating Point Adders. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:227-232 [Conf]
  51. Alberto Manzone, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Ernesto Sánchez, Matteo Sonza Reorda
    Integrating BIST Techniques for On-Line SoC Testing. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:235-240 [Conf]
  52. René Kothe, Christian Galke, Heinrich Theodor Vierhaus
    A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:241-246 [Conf]
  53. Michele Portolan, Régis Leveugle
    On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:247-252 [Conf]
  54. Erik Schüler, Luigi Carro
    Increasing Fault Tolerance to Multiple Upsets Using Digital Sigma-Delta Modulators. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:255-259 [Conf]
  55. Régis Leveugle
    A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:260-265 [Conf]
  56. Balkaran S. Gill, Michael Nicolaidis, Christos A. Papachristou
    Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:266-271 [Conf]
  57. Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy
    Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:275-280 [Conf]
  58. M. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira
    Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:281-286 [Conf]
  59. Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
    A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:287-292 [Conf]
  60. Yves Crouzet, Jacques Collet, Jean Arlat
    Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:295-298 [Conf]
  61. Christian Boleat, Gerard Colas
    Overview of Soft Errors Issues in Aerospace Systems. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:299-302 [Conf]
  62. Raoul Velazco, R. Ecoffet, F. Faure
    How to Characterize the Problem of SEU in Processors and Representative Errors Observed on Flight. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:303-308 [Conf]
  63. Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert
    Evaluation of SET and SEU Effects at Multiple Abstraction Levels. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:309-312 [Conf]
  64. Nicolas Renaud
    How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:313-314 [Conf]
  65. Michel Pignol
    How to Cope with SEU/SET at System Level?. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:315-318 [Conf]
  66. Andre L. R. Pouponnot
    Strategic Use of SEE Mitigation Techniques for the Development of the ESA Microprocessors: Past, Present and Future. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:319-323 [Conf]
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