Conferences in DBLP
Andrea Cuomo The Challenge of Reliability in Future Complex Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Norbert Seifert Extending Moore's Law into the next Decade - the SER Challenge. [Citation Graph (0, 0)][DBLP ] Conf ] Damien Leroy , Stanislaw J. Piestrak , Fabrice Monteiro , Abbas Dandache , Stéphane Rossignol , Pascal Moitrel Characterizing Laser-Induced Pulses in ICs: Methodology and Results. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , Martin Omaña , Daniele Rossi , José Manuel Cazeaux , T. M. Mak Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Marienfeld , Egor S. Sogomonyan , Vitalij Ocheretnij , Michael Gössel A New Self-Checking and Code-Disjoint Non-Restoring Array Divider. [Citation Graph (0, 0)][DBLP ] Conf ] Swaroop Ghosh , Swarup Bhunia , Arijit Raychowdhury , Kaushik Roy Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. [Citation Graph (0, 0)][DBLP ] Conf ] Chaowen Yu , Sudhakar M. Reddy , Irith Pomeranz A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Stelios Neophytou , Maria K. Michael , Spyros Tragoudas Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding. [Citation Graph (0, 0)][DBLP ] Conf ] G. Cellere , A. Paccagnella , A. Visconti , M. Bonanomi Erratic Effects of Irradiation in Floating Gate Memory Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Tino Heijmen , Damien Giot , Philippe Roche Factors That Impact the Critical Charge of Memory Elements. [Citation Graph (0, 0)][DBLP ] Conf ] G. Hubert , A. Bougerol , F. Miller , N. Buard , L. Anghel , T. Carriere , F. Wrobel , R. Gaillard Prediction of Transient Induced by Neutron/Proton in CMOS Combinational Logic Cells. [Citation Graph (0, 0)][DBLP ] Conf ] Rob Aitken Reliability Issues for Embedded SRAM at 90nm and Below. [Citation Graph (0, 0)][DBLP ] Conf ] Rochit Rajsuman Towards The Methodology of On-line Diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] T. M. Mak Test Challenges for 3D Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Marcello Coppola Trends and Trade-offs in Designing Highly Robust Throughput on Chip Communication Network. [Citation Graph (0, 0)][DBLP ] Conf ] Magdy S. Abadir Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Isaac Levendel The Consequences of Variability in Software. [Citation Graph (0, 0)][DBLP ] Conf ] Lorena Anghel , Michael Nicolaidis , Nadine Buard From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately? [Citation Graph (0, 0)][DBLP ] Conf ] Melanie Berg Fault Tolerance Implementation within SRAM Based FPGA Design Based upon the Increased Level of Single Event Upset Susceptibility. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Renaudin , Yannick Monnet Asynchronous Design: Fault Robustness and Security Characteristics. [Citation Graph (0, 0)][DBLP ] Conf ] André K. Nieuwland , Samir Jasarevic , Goran Jerin Combinational Logic Soft Error Analysis and Protection. [Citation Graph (0, 0)][DBLP ] Conf ] Sandip Kundu , Ilia Polian An Improved Technique for Reducing False Alarms Due to Soft Errors. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis A Low-Cost Single-Event Latchup Mitigation Sscheme. [Citation Graph (0, 0)][DBLP ] Conf ] David Hély , Frédéric Bancel , Marie-Lise Flottes , Bruno Rouzeyre Secure Scan Techniques: A Comparison. [Citation Graph (0, 0)][DBLP ] Conf ] Yannick Monnet , Marc Renaudin , Régis Leveugle , Nathalie Feyt , Pascal Moitrel , F. M'Buwa Nzenguet Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Konrad J. Kulikowski , Mark G. Karpovsky , Alexander Taubin Power Attacks on Secure Hardware Based on Early Propagation of Data. [Citation Graph (0, 0)][DBLP ] Conf ] Maico Cassel , Fernanda Lima Kastensmidt Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Cristian Grecu , André Ivanov , Res Saleh , Egor S. Sogomonyan , Partha Pratim Pande On-line Fault Detection and Location for NoC Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Ramtilak Vemu , Jacob A. Abraham CEDA: Control-flow Error Detection through Assertions. [Citation Graph (0, 0)][DBLP ] Conf ] V. Natarajan , G. Srinivasan , A. Chatterjee On-Line Error Detection in Wireless RF Transmitters Using Real-time Streaming Data. [Citation Graph (0, 0)][DBLP ] Conf ] Cristiano Lazzari , Ricardo A. L. Reis , Lorena Anghel Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Steffen Tarnick Embedded Borden 2-UED Code Checkers. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Breveglieri , Paolo Maistri , Israel Koren A Note on Error Detection in an RSA Architecture by Means of Residue Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Gian-Carlo Cardarilli , Marco Ottavi , Salvatore Pontarelli , Marco Re , Adelio Salsano Localization of Faults in Radix-n Signed Digit Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Galke , René Kothe , S. Schultke , K. Winkler , J. Honko , Heinrich Theodor Vierhaus Embedded Scan Test with Diagnostic Features for Self-Testing SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Mario García-Valderas , Marta Portela-García , Celia López-Ongil , Luis Entrena Emulation-based Fault Injection in Circuits with Embedded Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Pavel Kubalík , Petr Fiser , Hana Kubatova Fault Tolerant System Design Method Based on Self-Checking Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] S. Habermann , René Kothe , Heinrich Theodor Vierhaus Built-in Self Repair by Reconfiguration of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Sterpone , Massimo Violante Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur Pereira Frantz , Luigi Carro , Érika F. Cota , Fernanda Lima Kastensmidt Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitris Nikolos , Dimitrios Kagaris , S. Gidaros Diophantine-Equation Based Arithmetic Test Set Embedding. [Citation Graph (0, 0)][DBLP ] Conf ] Rodrigo Possamai Bastos , Fernanda Lima Kastensmidt , Ricardo Reis Design of a Robust 8-Bit Microprocessor to Soft Errors. [Citation Graph (0, 0)][DBLP ] Conf ] T. M. Mak , Subhasish Mitra Should Logic SER be Solved at the Circuit Level? [Citation Graph (0, 0)][DBLP ] Conf ] Michel Pignol DMT and DT2: Two Fault-Tolerant Architectures developed by CNES for COTs-based Spacecraft Supercomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Riccardo Mariani , Peter Fuhrmann , Boris Vittorelli Fault-Robust Microcontrollers for Automotive Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jacques Henri Collet , Piotr Zajac , Yves Crouzet , Andrzej Napieralski Contribution of Communications to Dependability in Massively-Defective General-Purpose Nanoarchitectures. [Citation Graph (0, 0)][DBLP ] Conf ] Matteo Sonza Reorda , Massimo Violante Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems. [Citation Graph (0, 0)][DBLP ] Conf ] P. Kenterlis , Nektarios Kranitis , Antonis M. Paschalis , Dimitris Gizopoulos , Mihalis Psarakis A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] André V. Fidalgo , Gustavo R. Alves , José M. Ferreira Real Time Fault Injection Using a Modified Debugging Infrastructure. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander V. Drozd , M. V. Lobachev , J. V. Drozd The Problem of On-Line Testing Methods In Approximate Data Processing. [Citation Graph (0, 0)][DBLP ] Conf ] M. Rodríguez-Irago , Juan J. Rodríguez-Andina , Fabian Vargas , Jorge Semião , Isabel C. Teixeira , João Paulo Teixeira Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Deepali Koppad , Danil Sokolov , Alexandre V. Bystrov , Alexandre Yakovlev Online Testing by Protocol Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Tino Heijmen Soft Error Rates in Deep-Submicron CMOS Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Günter Schindlbeck Trend in DRAM Soft Errors. [Citation Graph (0, 0)][DBLP ] Conf ] Daniele Rossi , Martin Omaña , Cecilia Metra , Andrea Pagni Checker No-Harm Alarm Robustness. [Citation Graph (0, 0)][DBLP ] Conf ] Frederic Worm , Patrick Thiran , Paolo Ienne Designing Robust Checkers in the Presence of Massive Timing Errors. [Citation Graph (0, 0)][DBLP ] Conf ] Petros Oikonomakos , Paul Fox Error Correction in Arithmetic Operations by I/O Inversion. [Citation Graph (0, 0)][DBLP ] Conf ] 