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Conferences in DBLP
- Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David A. Kranz, John Kubiatowicz, Beng-Hong Lim, Kenneth Mackenzie, Donald Yeung
The MIT Alewife Machine: Architecture and Performance. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:2-13 [Conf]
- Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi
The EM-X Parallel Computer: Architecture and Basic Performance. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:14-23 [Conf]
- Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Singh, Anoop Gupta
The SPLASH-2 Programs: Characterization and Methodological Considerations. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:24-36 [Conf]
- Håkan Grahn, Per Stenström
Efficient Strategies for Software-Only Protocols in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:38-47 [Conf]
- Alvin R. Lebeck, David A. Wood
Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:48-59 [Conf]
- Fredrik Dahlgren
Boosting the Performance of Hybrid Snooping Cache Protocols. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:60-69 [Conf]
- Andreas Nowatzyk, Michael C. Browne, Edmund J. Kelly, Michael Parkin
S-Connect: From Networks of Workstations to Supercomputer Performance. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:71-82 [Conf]
- Anujan Varma, Quinn Jacobson
Destage Algorithms for Disk Arrays with Non-Volatile Caches. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:83-95 [Conf]
- Gordon Stoll, Bin Wei, Douglas W. Clark, Edward W. Felten, Kai Li, Pat Hanrahan
Evaluating Multi-Port Frame Buffer Designs for a Mesh-Connected Multicomputer. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:96-105 [Conf]
- Andreas Nowatzyk, Paul R. Prucnal
Are Crossbars Really Dead? The Case for Optical Multiprocessor Interconnect Systems. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:106-115 [Conf]
- Stéphan Jourdan, Pascal Sainrat, Daniel Litaize
Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:117-125 [Conf]
- Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya
Unconstrained Speculative Execution with Predicated State Buffering. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:126-137 [Conf]
- Scott A. Mahlke, Richard E. Hank, James E. McCormick, David I. August, Wen-mei W. Hwu
A Comparison of Full and Partial Predicated Execution Support for ILP Processors. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:138-150 [Conf]
- Mike Simone, A. Essen, A. Ike, A. Krishnamoorthy, Tak Maruyama, Niteen Patkar, M. Ramaswami, Michael Shebanow, V. Thirumalaiswamy, DeForest Tovey
Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:151-162 [Conf]
- Trung A. Diep, Christopher Nelson, John Paul Shen
Performance Evaluation of the PowerPC 620 Microarchitecture. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:163-175 [Conf]
- Theodore H. Romer, Wayne H. Ohlrich, Anna R. Karlin, Brian N. Bershad
Reducing TLB and Memory Overhead Using Online Superpage Promotion. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:176-187 [Conf]
- Zheng Zhang, Josep Torrellas
Speeding Up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:188-199 [Conf]
- K. V. Anjan, Timothy Mark Pinkston
An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:201-210 [Conf]
- Kang G. Shin, Stuart W. Daniel
Analysis and implementation of hybrid switching. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:211-219 [Conf]
- Binh Vien Dao, José Duato, Sudhakar Yalamanchili
Configurable Flow Control Mechanisms for Fault-Tolerant Routing. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:220-229 [Conf]
- Timothy J. Callahan, Seth Copen Goldstein
NIFDY: A Low Overhead, High Throughput Network Interface. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:230-241 [Conf]
- Montse Peiron, Mateo Valero, Eduard Ayguadé, Tomás Lang
Vector Multiprocessors with Arbitrated Memory Access. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:243-252 [Conf]
- Krishna M. Kavi, Ali R. Hurson, Phenil Patadia, Elizabeth Abraham, Ponnarasu Shanmugam
Design of Cache Memories for Multi-Threaded Dataflow Architecture. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:253-264 [Conf]
- François Bodin, André Seznec
Skewed Associativity Enhances Performance Predictability. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:265-274 [Conf]
- Cliff Young, Nicholas C. Gloy, Michael D. Smith
A Comparative Analysis of Schemes for Correlated Branch Prediction. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:276-286 [Conf]
- Brad Calder, Dirk Grunwald
Next Cache Line and Set Prediction. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:287-296 [Conf]
- Vijay Karamcheti, Andrew A. Chien
A Comparison of Architectural Support for Messaging in the TMC CM-5 and the Cray T3D. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:298-307 [Conf]
- Thomas Stricker, Thomas R. Gross
Optimizing Memory System Performance for Communication in Parallel Computers. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:308-319 [Conf]
- Remzi H. Arpaci-Dusseau, David E. Culler, Arvind Krishnamurthy, Steve G. Steinberg, Katherine A. Yelick
Empirical Evaluation of the CRAY-T3D: A Compiler Perspective. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:320-331 [Conf]
- Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel
Optimization of Instruction Fetch Mechanisms for High Issue Rates. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:333-344 [Conf]
- Richard Uhlig, David Nagle, Trevor N. Mudge, Stuart Sechrest, Joel S. Emer
Instruction Fetching: Coping with Code Bloat. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:345-356 [Conf]
- Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grunwald
Instruction Cache Fetch Policies for Speculative Execution. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:357-367 [Conf]
- Todd M. Austin, Dionisios N. Pnevmatikatos, Gurindar S. Sohi
Streamlining Data Cache Access with Fast Address Calculation. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:369-380 [Conf]
- Hong Wang, Tong Sun, Qing Yang
CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:381-390 [Conf]
- Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
Simultaneous Multithreading: Maximizing On-Chip Parallelism. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:392-403 [Conf]
- Richard C. Ho, C. Han Yang, Mark Horowitz, David L. Dill
Architecture Validation for Processors. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:404-413 [Conf]
- Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar
Multiscalar Processors. [Citation Graph (0, 0)][DBLP]
ISCA, 1995, pp:414-425 [Conf]
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