Conferences in DBLP
David A. Patterson , Richard S. Piepho RISC assessment: A high-level language experiment. [Citation Graph (0, 0)][DBLP ] Conf ] Douglas W. Clark , Henry M. Levy Measurement and analysis of instruction use in the VAX-11/780. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna M. Kavi , Boumediene Belkhouche , Evelyn Bullard , Lois Delcambre , Stephen M. Nemecek HLL architectures: Pitfalls and predilections. [Citation Graph (0, 0)][DBLP ] Conf ] Allan Gottlieb , Ralph Grishman , Clyde P. Kruskal , Kevin P. McAuliffe , Larry Rudolph , Marc Snir The NYU Ultracomputer-designing a MIMD, shared-memory parallel machine (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] King-Hang Chu , King-sun Fu VLSI architectures for high speed recognition of context-free languages and finite-state languages. [Citation Graph (0, 0)][DBLP ] Conf ] Mark A. Franklin , Donald F. Wann Asynchronous and clocked control structures for VLSI based interconnection networks. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. McMillen , Howard Jay Siegel Performance and fault tolerance improvements in the Inverse Augmented Data Manipulator network. [Citation Graph (0, 0)][DBLP ] Conf ] D. S. Parker , C. S. Raghavendra The Gamma network: A multiprocessor interconnection network with redundant paths. [Citation Graph (0, 0)][DBLP ] Conf ] Roy M. Jenevein , James C. Browne A control processor for a reconfigurable array computer. [Citation Graph (0, 0)][DBLP ] Conf ] Laxmi N. Bhuyan , Dharma P. Agrawal A general class of processor interconnection strategies. [Citation Graph (0, 0)][DBLP ] Conf ] Forbes J. Burkowski Instruction set design issues relating to a static dataflow computer. [Citation Graph (0, 0)][DBLP ] Conf ] James E. Smith Decoupled access/execute computer architectures. [Citation Graph (0, 0)][DBLP ] Conf ] L. J. Caluwaerts , J. Debacker , J. A. Peperstraete A data flow architecture with a paged memory system. [Citation Graph (0, 0)][DBLP ] Conf ] B. Ramakrishna Rau , Christopher D. Glaeser , Raymond L. Picard Efficient code generation for horizontal architectures: Compiler techniques and architectural support. [Citation Graph (0, 0)][DBLP ] Conf ] Gene C. Barton Sentry: A novel hardware implementation of classic operating system mechanisms. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , Ytzhak H. Levendel , Premachandran R. Menon A logic simulation machine. [Citation Graph (0, 0)][DBLP ] Conf ] Subrata Dasgupta , Marius Olafsson Towards a family of languages for the design and implementation of machine architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Woei Lin , Chuan-lin Wu Design of a 2 × 2 fault-tolerant switching element. [Citation Graph (0, 0)][DBLP ] Conf ] Donald S. Fussell , Peter J. Varman Fault-tolerant wafer-scale architectures for VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Sakti Pramanik Database filters. [Citation Graph (0, 0)][DBLP ] Conf ] Mario Tokoro , Takashi Takizuka On the semantic structure of information - A proposal of the abstract storage architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Yasunori Dohi , Akira Suzuki , Noriyuki Matsui Hardware sorter and its application to data base machine. [Citation Graph (0, 0)][DBLP ] Conf ] Philip C. Treleaven , Richard P. Hopkins A recursive computer architecture for VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] M. Castan , Elliott I. Organick µ3L: An HLL-RISC processor for parallel execution of FP-language programs. [Citation Graph (0, 0)][DBLP ] Conf ] Ferdinand Hommes The heap/substitution concept - an implementation of functional operations on data structures for a reduction machine. [Citation Graph (0, 0)][DBLP ] Conf ] Paul F. Reynolds Jr. A shared resource algorithm for distributed simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Bijendra N. Jain Duplication of packets and their detection in X.25 communication protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Pauline Markenscoff A multiple processor system for real time control tasks. [Citation Graph (0, 0)][DBLP ] Conf ] Leslie Jill Miller A heterogeneous multiprocessor design and the distributed scheduling of its task group workload. [Citation Graph (0, 0)][DBLP ] Conf ] George H. Goble , Michael H. Marsh A dual processor VAX 11/780. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Dubois , Faye A. Briggs Effects of cache coherency in multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Trevor N. Mudge , B. A. Makrucki Probabilistic analysis of a crossbar switch. [Citation Graph (0, 0)][DBLP ] Conf ] Steven P. Levitan , Caxton C. Foster Finding an extremum in a network. [Citation Graph (0, 0)][DBLP ] Conf ] U. V. Premkumar , James C. Browne Resource allocation in rectangular SW banyans. [Citation Graph (0, 0)][DBLP ] Conf ] 