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Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
1988 (conf/isca/88)

  1. Joydeep Ghosh, Kai Hwang
    Critical Issues in Mapping Neural Networks on Message-Passing Multicomputers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:3-11 [Conf]
  2. Yoshiyasu Takefuji, Robert J. Jannarone, Yong B. Cho, Tatung Chen
    Multinomial Conjunctoid Statistical Learning Machines. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:12-17 [Conf]
  3. Ahmed Louri, Kai Hwang
    A Bit-Plane Architecture for Optical Computing with Two-Dimensional Symbolic Substitution. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:18-27 [Conf]
  4. Stuart Fiske, William J. Dally
    The Reconfigurable Arithmetic Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:30-36 [Conf]
  5. Andrew R. Pleszkun, Gurindar S. Sohi
    The Performance Potential of Multiple Functional Unit Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:37-44 [Conf]
  6. Wen-mei W. Hwu, Pohua P. Chang
    Exploiting Parallel Microprocessor Microarchitectures With a Compiler Code Generator. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:45-53 [Conf]
  7. Geoffrey D. McNiven, Edward S. Davidson
    Analysis of Memory Referencing Behavior For Design of Local Memories. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:56-63 [Conf]
  8. Richard J. Eickemeyer, Janak H. Patel
    Performance Evaluation of On-Chip Register and Cache Organizations. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:64-72 [Conf]
  9. Jean-Loup Baer, Wen-Hann Wang
    On the Inclusion Properties for Multi-Level Cache Hierarchies. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:73-80 [Conf]
  10. Robert T. Short, Henry M. Levy
    A Simulation Study of Two-Level Caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:81-88 [Conf]
  11. E. Chow, H. Madan, J. Peterson, Dirk Grunwald, Daniel A. Reed
    Hyperswitch Network for the Hypercube Computer. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:90-99 [Conf]
  12. Donald C. Winsor, Trevor N. Mudge
    Analysis of Bus Hierarchies for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:100-107 [Conf]
  13. Sizheng Wei, Gyungho Lee
    Extra Group Network: A Cost-Effective Fault-Tolerant Multistage Interconnection Network. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:108-115 [Conf]
  14. Hong Jiang, Kenneth C. Smith
    A Partial-Multiple-Bus Computer Structure with Improved Cost-Effectiveness. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:116-122 [Conf]
  15. Ian Watson, Viv Woods, Paul Watson, Richard Banach, Mark Greenberg, John Sargeant
    Flagship: A Parallel Architecture for Declarative Programming. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:124-130 [Conf]
  16. Robert A. Iannucci
    Toward a Dataflow/von Neumann Hybrid Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:131-140 [Conf]
  17. David E. Culler, Arvind
    Resource Requirements of Dataflow Programs. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:141-150 [Conf]
  18. Brinkley Sprunt, David Kirk, Lui Sha
    Priority-Driven, Preemptive I/O Controllers for Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:152-159 [Conf]
  19. Shridhar B. Shukla, Dharma P. Agrawal
    A Kernel-independent, Pipelined Architecture for Real-Time 2-D Convolution. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:160-166 [Conf]
  20. Wentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III
    Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:167-174 [Conf]
  21. Douglas W. Clark, Peter J. Bannon, James B. Keller
    Measuring VAX 8800 Performance with a Histogram Hardware Monitor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:176-185 [Conf]
  22. Richard L. Sites, Anant Agarwal
    Multiprocessor Cache Analysis Using ATUM. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:186-195 [Conf]
  23. Spencer W. Ng, Dorothy Lang, Robert Selinger
    Trade-offs Between Devices and Paths in Achieving Disk Interleaving. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:196-201 [Conf]
  24. K. Jainandunsing, Ed F. Deprettere
    Design of a Concurrent Computer for Solving Systems of Linear Equations. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:204-211 [Conf]
  25. Andrew Wolfe, Mauricio Breternitz Jr., Chriss Stephens, A. L. Ting, D. B. Kirk, Ronald P. Bianchini Jr., John Paul Shen
    The White Dwarf: A High-Performance Application-Specific Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:212-222 [Conf]
  26. Jean-Luc Gaudiot, C. M. Lin, M. Hosseiniyar
    Solving Partial Differential Equations in a Data-Driven Multiprocessor Environment. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:223-230 [Conf]
  27. De-Lei Lee
    Scrambled Storage for Parallel Memory Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:232-239 [Conf]
  28. Venkatesh Krishnaswamy, Sudhir Ahuja, Nicholas Carriero, David Gelernter
    The Architecture of a Linda Coprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:240-249 [Conf]
  29. H. T. Kung
    Deadlock Avoidance for Systolic Communication. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:252-260 [Conf]
  30. Kimming So, Vittorio Zecca
    Cache Performance of Vector Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:261-268 [Conf]
  31. Mary K. Vernon, Udi Manber
    Distributed Round-Robin and First-Come First-Serve Protocols and Their Application to Multiprocessor Bus Arbitration. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:269-277 [Conf]
  32. Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz
    An Evaluation of Directory Schemes for Cache Coherence. [Citation Graph (1, 0)][DBLP]
    ISCA, 1988, pp:280-289 [Conf]
  33. Steven A. Przybylski, Mark Horowitz, John L. Hennessy
    Performance Tradeoffs in Cache Design. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:290-298 [Conf]
  34. Hoichi Cheong, Alexander V. Veidenbaum
    A Cache Coherence Scheme With Fast Selective Invalidation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:299-307 [Conf]
  35. Mary K. Vernon, Edward D. Lazowska, John Zahorjan
    An Accurate and Efficient Performance Analysis Technique for Multiprocessor Snooping Cache-Consistency Protocols. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:308-315 [Conf]
  36. Darwen Rau, José A. B. Fortes, Howard Jay Siegel
    Destination Tag Routing Techniques Based on a State Model for the IADM Network. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:318-324 [Conf]
  37. Doug W. Kim, G. Jack Lipovski, Alfred C. Hartmann, Roy M. Jenevein
    Regular CC-Banyan Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:325-332 [Conf]
  38. Roy M. Jenevein, Thomas Mookken
    Traffic Analysis of Rectangular SW-Banyan Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:333-342 [Conf]
  39. Yuval Tamir, Gregory L. Frazier
    High-Performance Multi-Queue Buffers for VLSI Communication Switches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:343-354 [Conf]
  40. Bruno R. Preiss, V. Carl Hamacher
    A Cache-based Message Passing Scheme for a Shared-bus Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:358-364 [Conf]
  41. Taisuke Boku, Shigehiro Nomura, Hideharu Amano
    IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific Calculation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:365-372 [Conf]
  42. Susan J. Eggers, Randy H. Katz
    A Characterization of Sharing in Parallel Programs and Its Application to Coherency Protocol Evaluation. [Citation Graph (1, 0)][DBLP]
    ISCA, 1988, pp:373-382 [Conf]
  43. G. Jack Lipovski, Paul Vaughan
    A Fetch-And-Op Implementation for Parallel Computers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:384-392 [Conf]
  44. André Seznec, Yvon Jégou
    Synchronizing Processors Through Memory Requests in a Tightly Coupled Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:393-400 [Conf]
  45. Richard Fujimoto, Jya-Jang Tsai, Ganesh Gopalakrishnan
    Design and Performance of Special Purpose Hardware for Time Warp. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:401-408 [Conf]
  46. David R. Cheriton, Anoop Gupta, Patrick D. Boyle, Hendrik A. Goosen
    The VMP Multiprocessor: Initial Experience, Refinements and Performance Evlauation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:410-421 [Conf]
  47. James R. Goodman, Philip J. Woest
    The Wisconsin Multicube: A New Large-Scale Cache-Coherent Multiprocessor. [Citation Graph (1, 0)][DBLP]
    ISCA, 1988, pp:422-431 [Conf]
  48. Evan Tick
    Data Buffer Performance for Sequential Prolog Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:434-442 [Conf]
  49. Robert H. Halstead Jr., Tetsuya Fujita
    MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:443-451 [Conf]
  50. Philip L. Butler, J. D. Allen Jr., Donald W. Bouldin
    Parallel Architecture for OPS5. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:452-457 [Conf]
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