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Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
2003 (conf/isca/2003)

  1. Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan
    Temperature-Aware Microarchitecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:2-13 [Conf]
  2. Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steve Dropsho
    Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:14-25 [Conf]
  3. Ilhyun Kim, Mikko H. Lipasti
    Half-Price Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:28-38 [Conf]
  4. Il Park, Babak Falsafi, T. N. Vijaykumar
    Iimplicitly-Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:39-50 [Conf]
  5. Daniel Citron
    MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:52-59 [Conf]
  6. Jessica H. Tseng, Krste Asanovic
    Banked Multiported Register Files for High-Frequency Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:62-71 [Conf]
  7. Michael D. Powell, T. N. Vijaykumar
    Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:72-83 [Conf]
  8. Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe
    SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:84-95 [Conf]
  9. Mohamed Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar
    Transient-Fault Recovery for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:98-109 [Conf]
  10. Milos Prvulovic, Josep Torrellas
    ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:110-121 [Conf]
  11. Min Xu, Rastislav Bodík, Mark D. Hill
    A "Flight Data Recorder" for Enabling Full-System Multiprocessor Deterministic Replay. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:122-133 [Conf]
  12. Chuanjun Zhang, Frank Vahid, Walid A. Najjar
    A Highly-Configurable Cache Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:136-146 [Conf]
  13. Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose
    Energy Efficient Co-Adaptive Instruction Fetch and Issue. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:147-156 [Conf]
  14. Michael C. Huang, Jose Renau, Josep Torrellas
    Positional Adaptation of Processors: Application to Energy Reduction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:157-168 [Conf]
  15. Sudhanva Gurumurthi, Anand Sivasubramaniam, Mahmut T. Kandemir, Hubertus Franke
    DRPM: Dynamic Speed Control for Power Mangagement in Server Class Disks. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:169-179 [Conf]
  16. Milo M. K. Martin, Mark D. Hill, David A. Wood
    Token Coherence: Decoupling Performance and Correctness. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:182-193 [Conf]
  17. Arjun Singh, William J. Dally, Amit K. Gupta, Brian Towles
    GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:194-205 [Conf]
  18. Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood
    Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:206-217 [Conf]
  19. Zarka Cvetanovic
    Performance Analysis of the Alpha 21364-BAsed HP GS1280 Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:218-228 [Conf]
  20. Paramjit S. Oberoi, Gurindar S. Sohi
    Parallelism in the Front-End. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:230-240 [Conf]
  21. André Seznec, Antony Fraboulet
    Effective ahead Pipelining of Instruction Block Address Generation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:241-252 [Conf]
  22. Dan Ernst, Andrew Hamel, Todd M. Austin
    Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:253-262 [Conf]
  23. Ravi Bhargava, Lizy Kurian John
    Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:264-274 [Conf]
  24. Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
    Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:275-286 [Conf]
  25. Timothy Sherwood, George Varghese, Brad Calder
    A Pipelined Memory Architecture for High Throughput Network Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:288-299 [Conf]
  26. Jahangir Hasan, Satish Chandra, T. N. Vijaykumar
    Efficient Use of Memory Bandwidth to Improve Network Processor Throughput. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:300-311 [Conf]
  27. Renju Thomas, Manoj Franklin, Chris Wilkerson, Jared Stark
    Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global History. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:314-323 [Conf]
  28. Huiyang Zhou, Jill Flanagan, Thomas M. Conte
    Detecting Global Stride Locality in Value Streams. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:324-335 [Conf]
  29. Timothy Sherwood, Suleyman Sair, Brad Calder
    Phase Tracking and Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:336-347 [Conf]
  30. Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller
    Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:350-361 [Conf]
  31. Marc L. Corliss, E. Christopher Lewis, Amir Roth
    DISE: A Programmable Macro Engine for Customizing Applications. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:362-373 [Conf]
  32. Mark Oskin, Frederic T. Chong, Isaac L. Chuang, John Kubiatowicz
    Building Quantum Wires: The Long and the Short of It. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:374-385 [Conf]
  33. Zhenlin Wang, Doug Burger, Steven K. Reinhardt, Kathryn S. McKinley, Charles C. Weems
    Guided Region Prefetching: A Cooperative Hardware/Software Approach. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:388-398 [Conf]
  34. Christoforos E. Kozyrakis, David A. Patterson
    Overcoming the Limitations of Conventional Vector Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:399-409 [Conf]
  35. Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi Srinivasan, Matthew C. French
    A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:410-419 [Conf]
  36. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
    Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:422-433 [Conf]
  37. Michael K. Chen, Kunle Olukotun
    The Jrpm System for Dynamically Parallelizing Java Programs. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:434-445 [Conf]
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