Conferences in DBLP
Kevin Skadron , Mircea R. Stan , Wei Huang , Sivakumar Velusamy , Karthik Sankaranarayanan , David Tarjan Temperature-Aware Microarchitecture. [Citation Graph (0, 0)][DBLP ] Conf ] Grigorios Magklis , Michael L. Scott , Greg Semeraro , David H. Albonesi , Steve Dropsho Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Ilhyun Kim , Mikko H. Lipasti Half-Price Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Il Park , Babak Falsafi , T. N. Vijaykumar Iimplicitly-Multithreaded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Citron MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences. [Citation Graph (0, 0)][DBLP ] Conf ] Jessica H. Tseng , Krste Asanovic Banked Multiported Register Files for High-Frequency Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Michael D. Powell , T. N. Vijaykumar Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage. [Citation Graph (0, 0)][DBLP ] Conf ] Roland E. Wunderlich , Thomas F. Wenisch , Babak Falsafi , James C. Hoe SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. [Citation Graph (0, 0)][DBLP ] Conf ] Mohamed Gomaa , Chad Scarbrough , Irith Pomeranz , T. N. Vijaykumar Transient-Fault Recovery for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Milos Prvulovic , Josep Torrellas ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Min Xu , Rastislav Bodík , Mark D. Hill A "Flight Data Recorder" for Enabling Full-System Multiprocessor Deterministic Replay. [Citation Graph (0, 0)][DBLP ] Conf ] Chuanjun Zhang , Frank Vahid , Walid A. Najjar A Highly-Configurable Cache Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Alper Buyuktosunoglu , Tejas Karkhanis , David H. Albonesi , Pradip Bose Energy Efficient Co-Adaptive Instruction Fetch and Issue. [Citation Graph (0, 0)][DBLP ] Conf ] Michael C. Huang , Jose Renau , Josep Torrellas Positional Adaptation of Processors: Application to Energy Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Sudhanva Gurumurthi , Anand Sivasubramaniam , Mahmut T. Kandemir , Hubertus Franke DRPM: Dynamic Speed Control for Power Mangagement in Server Class Disks. [Citation Graph (0, 0)][DBLP ] Conf ] Milo M. K. Martin , Mark D. Hill , David A. Wood Token Coherence: Decoupling Performance and Correctness. [Citation Graph (0, 0)][DBLP ] Conf ] Arjun Singh , William J. Dally , Amit K. Gupta , Brian Towles GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Milo M. K. Martin , Pacia J. Harper , Daniel J. Sorin , Mark D. Hill , David A. Wood Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Zarka Cvetanovic Performance Analysis of the Alpha 21364-BAsed HP GS1280 Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Paramjit S. Oberoi , Gurindar S. Sohi Parallelism in the Front-End. [Citation Graph (0, 0)][DBLP ] Conf ] André Seznec , Antony Fraboulet Effective ahead Pipelining of Instruction Block Address Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Dan Ernst , Andrew Hamel , Todd M. Austin Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi Bhargava , Lizy Kurian John Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Balasubramonian , Sandhya Dwarkadas , David H. Albonesi Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy Sherwood , George Varghese , Brad Calder A Pipelined Memory Architecture for High Throughput Network Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Jahangir Hasan , Satish Chandra , T. N. Vijaykumar Efficient Use of Memory Bandwidth to Improve Network Processor Throughput. [Citation Graph (0, 0)][DBLP ] Conf ] Renju Thomas , Manoj Franklin , Chris Wilkerson , Jared Stark Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global History. [Citation Graph (0, 0)][DBLP ] Conf ] Huiyang Zhou , Jill Flanagan , Thomas M. Conte Detecting Global Stride Locality in Value Streams. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy Sherwood , Suleyman Sair , Brad Calder Phase Tracking and Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Aravindh Anantaraman , Kiran Seth , Kaustubh Patil , Eric Rotenberg , Frank Mueller Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Marc L. Corliss , E. Christopher Lewis , Amir Roth DISE: A Programmable Macro Engine for Customizing Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Oskin , Frederic T. Chong , Isaac L. Chuang , John Kubiatowicz Building Quantum Wires: The Long and the Short of It. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenlin Wang , Doug Burger , Steven K. Reinhardt , Kathryn S. McKinley , Charles C. Weems Guided Region Prefetching: A Cooperative Hardware/Software Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Christoforos E. Kozyrakis , David A. Patterson Overcoming the Limitations of Conventional Vector Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Jinwoo Suh , Eun-Gyu Kim , Stephen P. Crago , Lakshmi Srinivasan , Matthew C. French A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels. [Citation Graph (0, 0)][DBLP ] Conf ] Karthikeyan Sankaralingam , Ramadass Nagarajan , Haiming Liu , Changkyu Kim , Jaehyuk Huh , Doug Burger , Stephen W. Keckler , Charles R. Moore Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Michael K. Chen , Kunle Olukotun The Jrpm System for Dynamically Parallelizing Java Programs. [Citation Graph (0, 0)][DBLP ] Conf ] 