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Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
2004 (conf/isca/2004)

  1. Michael Bedford Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul Johnson, Jason Sungtae Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew Frank, Saman P. Amarasinghe, Anant Agarwal
    Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:2-13 [Conf]
  2. Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das
    Evaluating the Imagine Stream Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:14-25 [Conf]
  3. John W. Sias, Sain-zee Ueng, Geoff A. Kent, Ian M. Steiner, Erik M. Nystrom, Wen-mei W. Hwu
    Field-testing IMPACT EPIC research results in Itanium 2. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:26-39 [Conf]
  4. T. N. Vijaykumar, Zeshan Chishti
    Wire Delay is Not a Problem for SMT (In the Near Future). [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:40-51 [Conf]
  5. Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic
    The Vector-Thread Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:52-63 [Conf]
  6. Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas
    Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:64-75 [Conf]
  7. Yuan Chou, Brian Fahs, Santosh G. Abraham
    Microarchitecture Optimizations for Exploiting Memory-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:76-89 [Conf]
  8. Harold W. Cain, Mikko H. Lipasti
    Memory Ordering: A Value-Based Approach. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:90-101 [Conf]
  9. Lance Hammond, Vicky Wong, Michael K. Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, Kunle Olukotun
    Transactional Memory Coherence and Consistency. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:102-113 [Conf]
  10. Sudheendra Hangal, Durgam Vahia, Chaiyasit Manovit, Juin-Yeu Joseph Lu, Sridhar Narayanan
    TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:114-123 [Conf]
  11. Mainak Chaudhuri, Mark Heinrich
    SMTp: An Architecture for Next-generation Scalable Multi-threading. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:124-137 [Conf]
  12. Christopher J. Hughes, Sarita V. Adve
    A Formal Approach to Frequent Energy Adaptations for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:138-149 [Conf]
  13. John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong
    Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:150-161 [Conf]
  14. Roni Rosner, Yoav Almog, Micha Moffie, Naftali Schwartz, Avi Mendelson
    Power Awareness through Selective Dynamically Optimized Traces. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:162-175 [Conf]
  15. Lakshmi N. Bairavasundaram, Muthian Sivathanu, Andrea C. Arpaci-Dusseau, Remzi H. Arpaci-Dusseau
    X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDs. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:176-187 [Conf]
  16. Robert D. Mullins, Andrew West, Simon W. Moore
    Low-Latency Virtual-Channel Routers for On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:188-197 [Conf]
  17. Valentin Puente, José A. Gregorio, Fernando Vallejo, Ramón Beivide
    Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:198-211 [Conf]
  18. Alaa R. Alameldeen, David A. Wood
    Adaptive Cache Compression for High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:212-223 [Conf]
  19. Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas
    iWatcher: Efficient Architectural Support for Software Debugging. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:224-237 [Conf]
  20. Sami Yehia, Olivier Temam
    From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:238-249 [Conf]
  21. Ayose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero
    Prophet/Critic Hybrid Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:250-263 [Conf]
  22. Christopher Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt
    Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:264-275 [Conf]
  23. Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    The Case for Lifetime Reliability-Aware Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:276-287 [Conf]
  24. Michael D. Powell, T. N. Vijaykumar
    Exploiting Resonant Behavior to Reduce Inductive Noise. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:288-301 [Conf]
  25. J. Adam Butts, Gurindar S. Sohi
    Use-Based Register Caching with Decoupled Indexing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:302-313 [Conf]
  26. Rubén González, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero
    A Content Aware Integer Register File Organization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:314-324 [Conf]
  27. Mikko H. Lipasti, Brian R. Mestan, Erika Gunadi
    Physical Register Inlining. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:325-337 [Conf]
  28. Tejas Karkhanis, James E. Smith
    A First-Order Superscalar Processor Model. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:338-349 [Conf]
  29. Lieven Eeckhout, Robert H. Bell Jr., Bastiaan Stougie, Koen De Bosschere, Lizy Kurian John
    Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:350-363 [Conf]
  30. Bharath Iyer, Sadagopan Srinivasan, Bruce L. Jacob
    Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:364-375 [Conf]
  31. Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam
    A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:376-386 [Conf]
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