Conferences in DBLP
Michael Bedford Taylor , Walter Lee , Jason E. Miller , David Wentzlaff , Ian Bratt , Ben Greenwald , Henry Hoffmann , Paul Johnson , Jason Sungtae Kim , James Psota , Arvind Saraf , Nathan Shnidman , Volker Strumpen , Matthew Frank , Saman P. Amarasinghe , Anant Agarwal Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. [Citation Graph (0, 0)][DBLP ] Conf ] Jung Ho Ahn , William J. Dally , Brucek Khailany , Ujval J. Kapasi , Abhishek Das Evaluating the Imagine Stream Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] John W. Sias , Sain-zee Ueng , Geoff A. Kent , Ian M. Steiner , Erik M. Nystrom , Wen-mei W. Hwu Field-testing IMPACT EPIC research results in Itanium 2. [Citation Graph (0, 0)][DBLP ] Conf ] T. N. Vijaykumar , Zeshan Chishti Wire Delay is Not a Problem for SMT (In the Near Future). [Citation Graph (0, 0)][DBLP ] Conf ] Ronny Krashinsky , Christopher Batten , Mark Hampton , Steve Gerding , Brian Pharris , Jared Casper , Krste Asanovic The Vector-Thread Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Rakesh Kumar , Dean M. Tullsen , Parthasarathy Ranganathan , Norman P. Jouppi , Keith I. Farkas Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Yuan Chou , Brian Fahs , Santosh G. Abraham Microarchitecture Optimizations for Exploiting Memory-Level Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Harold W. Cain , Mikko H. Lipasti Memory Ordering: A Value-Based Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Lance Hammond , Vicky Wong , Michael K. Chen , Brian D. Carlstrom , John D. Davis , Ben Hertzberg , Manohar K. Prabhu , Honggo Wijaya , Christos Kozyrakis , Kunle Olukotun Transactional Memory Coherence and Consistency. [Citation Graph (0, 0)][DBLP ] Conf ] Sudheendra Hangal , Durgam Vahia , Chaiyasit Manovit , Juin-Yeu Joseph Lu , Sridhar Narayanan TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model. [Citation Graph (0, 0)][DBLP ] Conf ] Mainak Chaudhuri , Mark Heinrich SMTp: An Architecture for Next-generation Scalable Multi-threading. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher J. Hughes , Sarita V. Adve A Formal Approach to Frequent Energy Adaptations for Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] John Oliver , Ravishankar Rao , Paul Sultana , Jedidiah R. Crandall , Erik Czernikowski , Leslie W. Jones IV , Diana Franklin , Venkatesh Akella , Frederic T. Chong Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Roni Rosner , Yoav Almog , Micha Moffie , Naftali Schwartz , Avi Mendelson Power Awareness through Selective Dynamically Optimized Traces. [Citation Graph (0, 0)][DBLP ] Conf ] Lakshmi N. Bairavasundaram , Muthian Sivathanu , Andrea C. Arpaci-Dusseau , Remzi H. Arpaci-Dusseau X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDs. [Citation Graph (0, 0)][DBLP ] Conf ] Robert D. Mullins , Andrew West , Simon W. Moore Low-Latency Virtual-Channel Routers for On-Chip Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Valentin Puente , José A. Gregorio , Fernando Vallejo , Ramón Beivide Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism. [Citation Graph (0, 0)][DBLP ] Conf ] Alaa R. Alameldeen , David A. Wood Adaptive Cache Compression for High-Performance Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Pin Zhou , Feng Qin , Wei Liu , Yuanyuan Zhou , Josep Torrellas iWatcher: Efficient Architectural Support for Software Debugging. [Citation Graph (0, 0)][DBLP ] Conf ] Sami Yehia , Olivier Temam From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation. [Citation Graph (0, 0)][DBLP ] Conf ] Ayose Falcón , Jared Stark , Alex Ramírez , Konrad Lai , Mateo Valero Prophet/Critic Hybrid Branch Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher Weaver , Joel S. Emer , Shubhendu S. Mukherjee , Steven K. Reinhardt Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Jayanth Srinivasan , Sarita V. Adve , Pradip Bose , Jude A. Rivers The Case for Lifetime Reliability-Aware Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Michael D. Powell , T. N. Vijaykumar Exploiting Resonant Behavior to Reduce Inductive Noise. [Citation Graph (0, 0)][DBLP ] Conf ] J. Adam Butts , Gurindar S. Sohi Use-Based Register Caching with Decoupled Indexing. [Citation Graph (0, 0)][DBLP ] Conf ] Rubén González , Adrián Cristal , Daniel Ortega , Alexander V. Veidenbaum , Mateo Valero A Content Aware Integer Register File Organization. [Citation Graph (0, 0)][DBLP ] Conf ] Mikko H. Lipasti , Brian R. Mestan , Erika Gunadi Physical Register Inlining. [Citation Graph (0, 0)][DBLP ] Conf ] Tejas Karkhanis , James E. Smith A First-Order Superscalar Processor Model. [Citation Graph (0, 0)][DBLP ] Conf ] Lieven Eeckhout , Robert H. Bell Jr. , Bastiaan Stougie , Koen De Bosschere , Lizy Kurian John Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies. [Citation Graph (0, 0)][DBLP ] Conf ] Bharath Iyer , Sadagopan Srinivasan , Bruce L. Jacob Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs. [Citation Graph (0, 0)][DBLP ] Conf ] Angshuman Parashar , Sudhanva Gurumurthi , Anand Sivasubramaniam A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. [Citation Graph (0, 0)][DBLP ] Conf ] 