Conferences in DBLP
Richard N. Zucker , Jean-Loup Baer A Performance Study of Memory Consistency Models. [Citation Graph (0, 0)][DBLP ] Conf ] Peter J. Keleher , Alan L. Cox , Willy Zwaenepoel Lazy Release Consistency for Software Distributed Shared Memory. [Citation Graph (1, 0)][DBLP ] Conf ] Kourosh Gharachorloo , Anoop Gupta , John L. Hennessy Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Edil S. Tavares Fernandes , Fernando M. B. Barbosa Effects of Building Blocks on the Performance of Super-Scalar Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Monica S. Lam , Robert P. Wilson Limits of Control Flow on Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Franklin , Gurindar S. Sohi The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Litaize , Abdelaziz Mzoughi , Christine Rochange , Pascal Sainrat Towards a Shared-Memory Massively Parallel Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Per Stenström , Truman Joe , Anoop Gupta Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Lenoski , James Laudon , Truman Joe , David Nakahira , Luis Stevens , Anoop Gupta , John L. Hennessy The DASH Prototype: Implementation and Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Gideon D. Intrater , Ilan Y. Spillinger Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers. [Citation Graph (0, 0)][DBLP ] Conf ] J. Bradley Chen , Anita Borg , Norman P. Jouppi A Simulation Based Study of TLB Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Tse-Yu Yeh , Yale N. Patt Alternative Implementations of Two-Level Adaptive Branch Prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Hirata , Kozo Kimura , Satoshi Nagamine , Yoshiyuki Mochizuki , Akio Nishimura , Yoshimori Nakase , Teiji Nishizawa An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuhisa Sato , Yuetsu Kodama , Shuichi Sakai , Yoshinori Yamaguchi , Yasuhito Koumura Thread-based Programming for the EM-4 Hybrid Dataflow Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Rishiyur S. Nikhil , G. M. Papadopoulos , Arvind *T: A Multithreaded Massively Parallel Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Cezary Dubnicki , Thomas J. LeBlanc Adjustable Block Size Coherent Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Kunle Olukotun , Trevor N. Mudge , Richard B. Brown Performance Optimization of Pipelined Primary Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Scott McFarling Cache Replacement with Dynamic Exclusion. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen W. Keckler , William J. Dally Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism. [Citation Graph (0, 0)][DBLP ] Conf ] Bob Boothe , Abhiram G. Ranade Improved Multithreading Techniques for Hiding Communication Latency in Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro De Gloria , Paolo Faraboschi Instruction-level Parallelism in Prolog: Analysis and Architectural Support. [Citation Graph (0, 0)][DBLP ] Conf ] Lizy Kurian John , Paul T. Hulina , Lee D. Coraor Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module. [Citation Graph (0, 0)][DBLP ] Conf ] André Seznec , Jacques Lenfant Interleaved Parallel Schemes: Improving Memory Throughput on Supercomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Thorsten von Eicken , David E. Culler , Seth Copen Goldstein , Klaus E. Schauser Active Messages: A Mechanism for Integrated Communication and Computation. [Citation Graph (2, 0)][DBLP ] Conf ] Andrew A. Chien , Jae H. Kim Planar-Adaptive Routing: Low-cost Adaptive Networks for Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher J. Glass , Lionel M. Ni The Turn Model for Adaptive Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiyuki Shimizu , Takeshi Horie , Hiroaki Ishihata Low-Latency Message Communication Support for the AP1000. [Citation Graph (0, 0)][DBLP ] Conf ] Barbara P. Aichinger Futurebus+ as an I/O Bus: Profile B. [Citation Graph (1, 0)][DBLP ] Conf ] A. L. Narasimha Reddy A Study of I/O System Organizations. [Citation Graph (0, 0)][DBLP ] Conf ] Jai Menon , Dick Mattson Comparison of Sparing Alternatives for Disk Arrays. [Citation Graph (3, 0)][DBLP ] Conf ] Markus Siegle , Richard Hofmann Monitoring Program Behaviour on SUPRENUM. [Citation Graph (0, 0)][DBLP ] Conf ] Todd M. Austin , Gurindar S. Sohi Dynamic Dependency Analysis of Ordinary Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Walid A. Najjar , William Marcus Miller , A. P. Wim Böhm An Analysis of Loop Latency in Dataflow Execution. [Citation Graph (0, 0)][DBLP ] Conf ] Qing Yang , Liping Wu Yang A Novel Cache Design for Vector Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Mateo Valero , Tomás Lang , José M. Llabería , Montse Peiron , Eduard Ayguadé , Juan J. Navarro Increasing the Number of Strides for Conflict-Free Vector Access. [Citation Graph (0, 0)][DBLP ] Conf ] William A. Wulf Evaluation of the WM Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Kirk L. Johnson The Impact of Communication Locality on Large-Scale Multiprocessor Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Steven L. Scott , James R. Goodman , Mary K. Vernon Performance of the SCI Ring. [Citation Graph (1, 0)][DBLP ] Conf ] Madhusudhan Talluri , Shing I. Kong , Mark D. Hill , David A. Patterson Tradeoffs in Supporting Two Page Sizes. [Citation Graph (0, 0)][DBLP ] Conf ] 