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Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
2005 (conf/isca/2005)

  1. Ruby B. Lee, Peter C. S. Kwan, John Patrick McGregor, Jeffrey Dwoskin, Zhenghong Wang
    Architecture for Protecting Critical Secrets in Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:2-13 [Conf]
  2. Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Chenghuai Lu, Alexandra Boldyreva
    High Efficiency Counter Mode Security Architecture via Prediction and Precomputation. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:14-24 [Conf]
  3. G. Edward Suh, Charles W. O'Donnell, Ishan Sachdev, Srinivas Devadas
    Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:25-36 [Conf]
  4. Sudhanva Gurumurthi, Anand Sivasubramaniam, Vivek K. Natarajan
    Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal Management. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:38-49 [Conf]
  5. Ram Huggahalli, Ravi R. Iyer, Scott Tetrick
    Direct Cache Access for High Bandwidth Network I/O. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:50-59 [Conf]
  6. Haryadi S. Gunawi, Nitin Agrawal, Andrea C. Arpaci-Dusseau, Remzi H. Arpaci-Dusseau, Jiri Schindler
    Deconstructing Commodity Storage Clusters. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:60-71 [Conf]
  7. Magnus Ekman, Per Stenström
    A Robust Main-Memory Compression Scheme. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:74-85 [Conf]
  8. Brian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steven S. Lumetta
    Continuous Optimization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:86-97 [Conf]
  9. Vlad Petric, Tingting Sha, Amir Roth
    RENO - A Rename-Based Instruction Optimizer. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:98-109 [Conf]
  10. Lin Tan, Timothy Sherwood
    A High Throughput String Matching Architecture for Intrusion Detection and Prevention. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:112-122 [Conf]
  11. Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Sumeet Singh
    A Tree Based Router Search Engine Architecture with Single Port Memories. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:123-133 [Conf]
  12. Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai
    An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:134-145 [Conf]
  13. George A. Reis, Jonathan Chang, Neil Vachharajani, Ram Rangan, David I. August, Shubhendu S. Mukherjee
    Design and Evaluation of Hybrid Fault-Detection Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:148-159 [Conf]
  14. Ethan Schuchman, T. N. Vijaykumar
    Rescue: A Microarchitecture for Testability and Defect Tolerance. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:160-171 [Conf]
  15. Mohamed A. Gomaa, T. N. Vijaykumar
    Opportunistic Transient-Fault Detection. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:172-183 [Conf]
  16. Steven Balensiefer, Lucas Kregor-Stickles, Mark Oskin
    An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:186-196 [Conf]
  17. Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David Blaauw
    Energy Optimization of Subthreshold-Voltage Sensor Network Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:197-207 [Conf]
  18. Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei, David Brooks
    An Ultra Low Power System Architecture for Sensor Network Applications. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:208-219 [Conf]
  19. Thomas F. Wenisch, Stephen Somogyi, Nikolaos Hardavellas, Jangwoo Kim, Anastassia Ailamaki, Babak Falsafi
    Temporal Streaming of Shared Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:222-233 [Conf]
  20. Andreas Moshovos
    RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:234-245 [Conf]
  21. Jason F. Cantin, Mikko H. Lipasti, James E. Smith
    Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:246-257 [Conf]
  22. Stephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley
    Improving Program Efficiency by Packing Instructions into Registers. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:260-271 [Conf]
  23. Nathan Clark, Jason A. Blome, Michael L. Chu, Scott A. Mahlke, Stuart Biles, Krisztián Flautner
    An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:272-283 [Conf]
  24. Satish Narayanasamy, Gilles Pokam, Brad Calder
    BugNet: Continuously Recording Program Execution for Deterministic Replay Debugging. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:284-295 [Conf]
  25. Murali Annavaram, Ed Grochowski, John Paul Shen
    Mitigating Amdahl's Law through EPI Throttling. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:298-309 [Conf]
  26. Emil Talpes, Diana Marculescu
    Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:310-321 [Conf]
  27. Vlad Petric, Amir Roth
    Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:322-333 [Conf]
  28. Michael Zhang, Krste Asanovic
    Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:336-345 [Conf]
  29. Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishnan Rajamony
    Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:346-356 [Conf]
  30. Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar
    Optimizing Replication, Communication, and Capacity Allocation in CMPs. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:357-368 [Conf]
  31. Onur Mutlu, Hyesoon Kim, Yale N. Patt
    Techniques for Efficient Processing in Runahead Execution Engines. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:370-381 [Conf]
  32. Daniel A. Jiménez
    Piecewise Linear Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:382-393 [Conf]
  33. André Seznec
    Analysis of the O-GEometric History Length Branch Predictor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:394-405 [Conf]
  34. Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
    Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:408-419 [Conf]
  35. John Kim, William J. Dally, Brian Towles, Amit K. Gupta
    Microarchitecture of a High-Radix Router. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:420-431 [Conf]
  36. Daeho Seo, Akif Ali, Won-Taek Lim, Nauman Rafique, Mithuna Thottethodi
    Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:432-443 [Conf]
  37. Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, Konrad K. Lai
    Scalable Load and Store Processing in Latency Tolerant Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:446-457 [Conf]
  38. Amir Roth
    Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:458-468 [Conf]
  39. Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería
    Store Buffer Design in First-Level Multibanked Data Caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:469-480 [Conf]
  40. Albert Meixner, Daniel J. Sorin
    Dynamic Verification of Sequential Consistency. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:482-493 [Conf]
  41. Ravi Rajwar, Maurice Herlihy, Konrad K. Lai
    Virtualizing Transactional Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:494-505 [Conf]
  42. Saisanthosh Balakrishnan, Ravi Rajwar, Michael Upton, Konrad K. Lai
    The Impact of Performance Asymmetry in Emerging Multicore Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:506-517 [Conf]
  43. Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers
    Exploiting Structural Duplication for Lifetime Reliability Enhancement. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:520-531 [Conf]
  44. Arijit Biswas, Paul Racunas, Razvan Cheveresan, Joel S. Emer, Shubhendu S. Mukherjee, Ram Rangan
    Computing Architectural Vulnerability Factors for Address-Based Structures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:532-543 [Conf]
  45. Moinuddin K. Qureshi, David Thompson, Yale N. Patt
    The V-Way Cache: Demand Based Associativity via Global Replacement. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:544-555 [Conf]
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