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Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
1993 (conf/isca/93)

  1. Robert Cypher, Alex Ho, Smaragda Konstantinidou, Paul Messina
    Architectural Requirements of Parallel Scientific Applications with Explicit Communication. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:2-13 [Conf]
  2. Edward Rothberg, Jaswinder Pal Singh, Anoop Gupta
    Working Sets, Cache Sizes, and Node Granularity Issues for Large-Scale Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:14-25 [Conf]
  3. David Nagle, Richard Uhlig, Tim Stanley, Stuart Sechrest, Trevor N. Mudge, Richard B. Brown
    Design Tradeoffs for Software-Managed TLBs. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:27-38 [Conf]
  4. Jerome C. Huck, Jim Hays
    Architectural Support for Translation Table Management in Large Address Space Machines. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:39-50 [Conf]
  5. Pei Cao, Swee Boon Lim, Shivakumar Venkataraman, John Wilkes
    The TickerTAIP Parallel RAID Architecture. [Citation Graph (1, 0)][DBLP]
    ISCA, 1993, pp:52-63 [Conf]
  6. Daniel Stodolsky, Garth A. Gibson, Mark Holland
    Parity Logging Overcoming the Small Write Problem in Redundant Disk Arrays. [Citation Graph (9, 0)][DBLP]
    ISCA, 1993, pp:64-75 [Conf]
  7. Jai Menon, Jim Cortney
    The Architecture of a Fault-Tolerant Cached RAID Controller. [Citation Graph (6, 0)][DBLP]
    ISCA, 1993, pp:76-86 [Conf]
  8. Michel Dubois, Jonas Skeppstedt, Livio Ricciulli, Krishnan Ramamurthy, Per Stenström
    The Detection and Elimination of Useless Misses in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:88-97 [Conf]
  9. Alan L. Cox, Robert J. Fowler
    Adaptive Cache Coherency for Detecting Migratory Shared Data. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:98-108 [Conf]
  10. Per Stenström, Mats Brorsson, Lars Sandberg
    An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:109-118 [Conf]
  11. Carl A. Waldspurger, William E. Weihl
    Register Relocation: Flexible Contexts for Multithreading. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:120-130 [Conf]
  12. Yasuo Hidaka, Hanpei Koike, Hidehiko Tanaka
    Multiple Threads in Cyclic Register Windows. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:131-142 [Conf]
  13. Sandhya Dwarkadas, Peter J. Keleher, Alan L. Cox, Willy Zwaenepoel
    Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network Technology. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:144-155 [Conf]
  14. David A. Wood, Satish Chandra, Babak Falsafi, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, Shubhendu S. Mukherjee, Subbarao Palacharla, Steven K. Reinhardt
    Mechanisms for Cooperative Shared Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:156-167 [Conf]
  15. André Seznec
    A Case for Two-Way Skewed-Associative Caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:169-178 [Conf]
  16. Anant Agarwal, Steven D. Pudar
    Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:179-190 [Conf]
  17. Norman P. Jouppi
    Cache Write Policies and Performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:191-201 [Conf]
  18. Eric L. Boyd, Edward S. Davidson
    Hierarchical Performance Modeling with MACS: A Case Study of the Convex C-240. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:203-212 [Conf]
  19. David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu, Alexander V. Veidenbaum, Jeff Konicek, Pen-Chung Yew, Kyle Gallivan, William Jalby, Harry A. G. Wijshoff, Randall Bramley, U. M. Yang, Perry A. Emrath, David A. Padua, Rudolf Eigenmann, Jay Hoeflinger, Greg Jaxon, Zhiyuan Li, T. Murphy, John T. Andrews, Stephen W. Turner
    The Cedar System and an Initial Performance Study. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:213-223 [Conf]
  20. Michael D. Noakes, Deborah A. Wallach, William J. Dally
    The J-Machine Multicomputer: An Architectural Evaluation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:224-235 [Conf]
  21. John Bunda, Donald S. Fussell, Roy M. Jenevein, William C. Athas
    16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:237-246 [Conf]
  22. Tokuzo Kiyohara, Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Sadun Anik, Wen-mei W. Hwu
    Register Connection: A New Approach to Adding Registers into Instruction Set Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:247-256 [Conf]
  23. Tse-Yu Yeh, Yale N. Patt
    A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:257-266 [Conf]
  24. Luiz André Barroso, Michel Dubois
    The Performance of Cache-Coherent Ring-based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:268-277 [Conf]
  25. Dean M. Tullsen, Susan J. Eggers
    Limitations of Cache Prefetching on a Bus-Based Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:278-288 [Conf]
  26. Maurice Herlihy, J. Eliot B. Moss
    Transactional Memory: Architectural Support for Lock-Free Data Structures. [Citation Graph (1, 0)][DBLP]
    ISCA, 1993, pp:289-300 [Conf]
  27. Ellen Spertus, Seth Copen Goldstein, Klaus E. Schauser, Thorsten von Eicken, David E. Culler, William J. Dally
    Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:302-313 [Conf]
  28. Takeshi Horie, Kenichi Hayashi, Toshiyuki Shimizu, Hiroaki Ishihata
    Improving AP1000 Parallel Computer Performance with Message Communication. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:314-325 [Conf]
  29. Wei-Chung Hsu, James E. Smith
    Performance of Cached DRAM Organizations in Vector Supercomputers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:327-336 [Conf]
  30. Q. S. Gao
    The Chinese Remainder Theorem and the Prime Memory System. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:337-340 [Conf]
  31. André Seznec, Jacques Lenfant
    Odd Memory Systems May be Quite Interesting. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:341-350 [Conf]
  32. Rajendra V. Boppana, Suresh Chalasani
    A Comparison of Adaptive Wormhole Routing Algorithms. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:351-360 [Conf]
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