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Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
1990 (conf/isca/90)

  1. Sarita V. Adve, Mark D. Hill
    Weak Ordering - A New Definition. [Citation Graph (1, 0)][DBLP]
    ISCA, 1990, pp:2-14 [Conf]
  2. Kourosh Gharachorloo, Daniel Lenoski, James Laudon, Phillip B. Gibbons, Anoop Gupta, John L. Hennessy
    Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors. [Citation Graph (1, 0)][DBLP]
    ISCA, 1990, pp:15-26 [Conf]
  3. Joonwon Lee, Umakishore Ramachandran
    Synchronization with Multiprocessor Caches. [Citation Graph (1, 0)][DBLP]
    ISCA, 1990, pp:27-37 [Conf]
  4. Po-Jen Chuang, Nian-Feng Tzeng
    Dynamic Processor Allocation in Hypercube Computers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:40-49 [Conf]
  5. Abdou Youssef, Bruce W. Arden
    A New Approach to Fast Control of r2 x r2 3-Stage Benes Networks of r x r Crossbar Switches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:50-59 [Conf]
  6. William J. Dally
    Virtual-Channel Flow Control. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:60-68 [Conf]
  7. Shekhar Borkar, Robert Cohn, George W. Cox, Thomas R. Gross, H. T. Kung, Monica S. Lam, Margie Levine, Brian Moore, Wire Moore, Craig Peterson, Jim Susman, Jim Sutton, John Urbanski, Jon A. Webb
    Supporting Systolic and Memory Communciation in iWarp. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:70-81 [Conf]
  8. Gregory M. Papadopoulos, David E. Culler
    Monsoon: An Explicit Token-Store Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:82-91 [Conf]
  9. Marco Annaratone, Marco Fillo, Kiyoshi Nakabayashi, Marc A. Viredaz
    The K2 Parallel Processor: Architecture and Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:92-101 [Conf]
  10. Anant Agarwal, Beng-Hong Lim, David A. Kranz, John Kubiatowicz
    APRIL: A Processor Architecture for Multiprocessing. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:104-114 [Conf]
  11. Roberto Bisiani, Mosur Ravishankar
    PLUS: A Distributed Shared-Memory System. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:115-124 [Conf]
  12. John K. Bennett, John B. Carter, Willy Zwaenepoel
    Adaptive Software Cache Management for Distributed Shared Memory Architectures. [Citation Graph (2, 0)][DBLP]
    ISCA, 1990, pp:125-134 [Conf]
  13. Brian W. O'Krafka, A. Richard Newton
    An Empirical Evaluation of Two Memory-Efficient Directory Methods. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:138-147 [Conf]
  14. Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Anoop Gupta, John L. Hennessy
    The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:148-159 [Conf]
  15. Steven A. Przybylski
    The Performance Impact of Block Sizes and Fetch Strategies. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:160-169 [Conf]
  16. D. Alpert, A. Averbuch, O. Danieli
    Performance Comparison of Load/Store and Symmetric Instruction Set Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:172-181 [Conf]
  17. Jack W. Davidson, David B. Whalley
    Reducing the Cost of Branches by Using Registers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:182-191 [Conf]
  18. Carl E. Love, Harry F. Jordan
    An Investigation of Static Versus Dynamic Scheduling. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:192-201 [Conf]
  19. Dileep Bhandarkar, Richard Brunner
    VAX Vector Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:204-215 [Conf]
  20. Robert W. Horst, Richard L. Harris, Robert L. Jardine
    Multiple Instruction Issue in the NonStop Cyclone Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:216-226 [Conf]
  21. Shreekant S. Thakkar, Mark Sweiger
    Performance of an OLTP Application on Symmetry Multiprocessor System. [Citation Graph (5, 0)][DBLP]
    ISCA, 1990, pp:228-238 [Conf]
  22. Ding-Kai Chen, Hong-Men Su, Pen-Chung Yew
    The Impact of Synchronization and Granularity on Parallel Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:239-248 [Conf]
  23. Hakon O. Bugge, Ernst H. Kristiansen, Bjorn O. Bakka
    Trace-Driven Simulations for a Two-Level Cache Design in Open Bus Systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:250-259 [Conf]
  24. Jiun-Ming Hsu, Prithviraj Banerjee
    Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:260-269 [Conf]
  25. Anita Borg, Richard E. Kessler, David W. Wall
    Generation and Analysis of Very Long Address Traces. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:270-279 [Conf]
  26. Bruce K. Holmer, Barton Sano, Michael J. Carlton, Peter Van Roy, Ralph Clarke Haygood, William R. Bush, Alvin M. Despain, Joan M. Pendleton, Tep P. Dobry
    Fast Prolog with an Extended General Purpose Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:282-291 [Conf]
  27. Leon Alkalaj, Tomás Lang, Milos D. Ercegovac
    Architectural Support for the Management of Tightly-Coupled Fine-Grain Goals in Flat Concurrent Prolog. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:292-301 [Conf]
  28. Samuel Ho, Lawrence Snyder
    Balance in Architectural Design. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:302-310 [Conf]
  29. A. L. Narasimha Reddy, Prithviraj Banerjee
    A Study of I/O Behavior of Perfect Benchmarks on a Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:312-321 [Conf]
  30. Peter M. Chen, David A. Patterson
    Maximizing Performance in a Striped Disk Array. [Citation Graph (6, 0)][DBLP]
    ISCA, 1990, pp:322-331 [Conf]
  31. Kang G. Shin, Greg Dykema
    A Distributed I/O Architecture for HARTS. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:332-342 [Conf]
  32. Michael D. Smith, Monica S. Lam, Mark Horowitz
    Boosting Beyond Static Scheduling in a Superscalar Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:344-354 [Conf]
  33. George Taylor, Peter Davies, Michael Farmwald
    The TLB Slice - A Low-Cost High-Speed Address Translation Mechanism. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:355-363 [Conf]
  34. Norman P. Jouppi
    Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:364-373 [Conf]
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