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International Symposium om Computer Architecture (ISCA) (isca)
1998 (conf/isca/98)

  1. G. Jack Lipovski
    Retrospective: Banyan Networks for Partitioning Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:1- [Conf]
  2. Jack B. Dennis
    Retrospective: A Preliminary Architecture for a Basic Data Flow Processor. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:2-4 [Conf]
  3. Luiz André Barroso, Kourosh Gharachorloo, Edouard Bugnion
    Memory System Characterization of Commercial Workloads. [Citation Graph (1, 0)][DBLP]
    ISCA, 1998, pp:3-14 [Conf]
  4. Janak H. Patel
    Retrospective: Improving the Throughput of a Pipeline by Insertion of Delays. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:5- [Conf]
  5. Gordon Bell, William D. Strecker
    Retrospective: What Have We Learned from the PDP-11 - What We Have Learned from VAX and Alpha. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:6-10 [Conf]
  6. Leonard J. Shustek, Bernard L. Peuto
    Retrospective: An Instruction Timing Model of CPU Performance. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:11-12 [Conf]
  7. David R. Ditzel, David A. Patterson
    Retrospective: A Retrospective on High-Level Language Computer Architecture. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:13-14 [Conf]
  8. Kenneth E. Batcher
    Retrospective: Architecture of a Massively Parallel Processor. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:15-16 [Conf]
  9. Kimberly Keeton, David A. Patterson, Yong Qiang He, Roger C. Raphael, Walter E. Baker
    Performance Characterization of a Quad Pentium Pro SMP using OLTP Workloads. [Citation Graph (2, 0)][DBLP]
    ISCA, 1998, pp:15-26 [Conf]
  10. Kenneth A. Pier
    Retrospective: A Processor for a High-Performance Personal Computer. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:17-19 [Conf]
  11. David Kroft
    Retrospective: Lockup-Free Instruction Fetch/Prefetch Cache Organization. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:20-21 [Conf]
  12. James E. Smith
    Retrospective: A Study of Branch Prediction Strategies. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:22-23 [Conf]
  13. David A. Patterson, Carlo H. Séquin
    Retrospective: RISC I: A Reduced Instruction Set Computer. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:24-26 [Conf]
  14. James E. Smith
    Retrospective: Decoupled Access/Execute Architectures. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:27-28 [Conf]
  15. Dennis C. Lee, Patrick Crowley, Jean-Loup Baer, Thomas E. Anderson, Brian N. Bershad
    Execution Characteristics of Desktop Applications on Windows NT. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:27-38 [Conf]
  16. Allan Gottlieb
    Retrospective: A Personal Retrospective on the NYU Ultracomputer. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:29-31 [Conf]
  17. James R. Goodman
    Retrospective: Using Cache Memory to Reduce Processor-Memory Traffic. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:32-33 [Conf]
  18. Joseph A. Fisher
    Retrospective: Very Long Instruction Word Architectures and the ELI-512. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:34-36 [Conf]
  19. Joel S. Emer, Douglas W. Clark
    Retrospective: Characterization of Processor Performance in the VAX-11/780. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:37-38 [Conf]
  20. Janak H. Patel
    Retrospective: A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:39-41 [Conf]
  21. Jack L. Lo, Luiz André Barroso, Susan J. Eggers, Kourosh Gharachorloo, Henry M. Levy, Sujay S. Parekh
    An Analysis of Database Workload Performance on Simultaneous Multithreaded Processors. [Citation Graph (1, 0)][DBLP]
    ISCA, 1998, pp:39-50 [Conf]
  22. James E. Smith
    Retrospective: Implementing Precise Interrupts in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:42- [Conf]
  23. Wen-mei W. Hwu, Yale N. Patt
    Retrospective: HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:43-44 [Conf]
  24. Thomas R. Gross, Monica S. Lam
    Retrospective: A Retrospective on the Warp Machines. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:45-47 [Conf]
  25. Michel Dubois, Christoph Scheurich
    Retrospective: Memory Access Buffering in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:48-50 [Conf]
  26. Gurindar S. Sohi
    Retrospective: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:51-53 [Conf]
  27. Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt
    An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:52-61 [Conf]
  28. William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, Ellen Spertus, Deborah A. Wallach, D. Scott Wills, Andrew Chang, John S. Keen
    Retrospective: the J-machine. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:54-58 [Conf]
  29. Jean-Loup Baer, Wen-Hann Wang
    Retrospective: On the Inclusion Properties for Multi-Level Cache Hierarchies. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:59-60 [Conf]
  30. John L. Hennessy
    Retrospective: Evaluation of Directory Dchemes for Cache Coherence. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:61-62 [Conf]
  31. Eitan Federovsky, Meir Feder, Shlomo Weiss
    Branch Prediction Based on Universal Data Compression Algorithms. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:62-72 [Conf]
  32. Sarita V. Adve, Mark D. Hill
    Retrospective: Weak Ordering - A New Definition. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:63-66 [Conf]
  33. Kourosh Gharachorloo
    Retrospective: Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:67-70 [Conf]
  34. Norman P. Jouppi
    Retrospective: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:71-73 [Conf]
  35. Yiannakis Sazeides, James E. Smith
    Modeling Program Predictability. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:73-84 [Conf]
  36. David E. Culler, Gregory M. Papadopoulos
    Retrospective: Monsoon: An Explicit Token-Store Architecture. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:74-76 [Conf]
  37. Wen-mei W. Hwu
    Retrospective: IMPACT: An Architectural Framework for Multiple-Instruction Issue. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:77-79 [Conf]
  38. Daniel Lenoski, James Laudon
    Retrospective: The DASH Prototype: Implementation and Performance. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:80-82 [Conf]
  39. Thorsten von Eicken, David E. Culler, Klaus E. Schauser, Seth Copen Goldstein
    Retrospective: Active Messages: A Mechanism for Integrating Computation and Communication. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:83-84 [Conf]
  40. Lionel M. Ni
    Retrospective: The Turn Model for Adaptive Routing. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:85-86 [Conf]
  41. Michael Cox, Narendra Bhandri, Michael Shantz
    Multi-Level Texture Caching for 3D Graphics Hardware. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:86-97 [Conf]
  42. Tse-Yu Yeh, Yale N. Patt
    Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:87-88 [Conf]
  43. Alexander V. Veidenbaum, Pen-Chung Yew, David J. Kuck, Constantine D. Polychronopoulos, David A. Padua, Edward S. Davidson, Kyle Gallivan
    Retrospective: The Cedar System. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:89-91 [Conf]
  44. Matthias A. Blumrich, Kai Li, Richard Alpert, Cezary Dubnicki, Edward W. Felten, Jonathan Sandberg
    Retrospective: Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:92-94 [Conf]
  45. Jeffrey Kuskin
    Retrospective: The Stanford FLASH Multiprocessor. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:95-97 [Conf]
  46. Hans Eberle, Erwin Oertli
    Switcherland: A QoS Communication Architecture for Workstation Clusters. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:98-108 [Conf]
  47. Steven K. Reinhardt, James R. Larus, David A. Wood
    Retrospective: Tempest and Typhoon: User-Level Shared Memory. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:98-102 [Conf]
  48. Anant Agarwal
    Retrospective: The MIT Alewife Machine: Architecture and Performance. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:103-110 [Conf]
  49. Guillermo A. Alvarez, Walter A. Burkhard, Larry J. Stockmeyer, Flaviu Cristian
    Declustered Disk Array Architectures with Optimal and Near-Optimal Parallelism. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:109-120 [Conf]
  50. Gurindar S. Sohi
    Retrospective: Multiscalar Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:111-114 [Conf]
  51. Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
    Retrospective: Simultaneous Multithreading: Maximizing On-Chip Parallelism. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:115-116 [Conf]
  52. L. Rodney Goke, G. Jack Lipovski
    Banyan Networks for Partitioning Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:117-124 [Conf]
  53. Dirk Grunwald, Artur Klauser, Srilatha Manne, Andrew R. Pleszkun
    Confidence Estimation for Speculation Control. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:122-131 [Conf]
  54. Jack B. Dennis, David Misunas
    A Primlinary Architecture for a Basic Data-Flow Processor. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:125-131 [Conf]
  55. Janak H. Patel, Edward S. Davidson
    Improving the Throughput of a Pipeline by Insertion of Delays. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:132-137 [Conf]
  56. Srilatha Manne, Artur Klauser, Dirk Grunwald
    Pipeline Gating: Speculation Control for Energy Reduction. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:132-141 [Conf]
  57. Gordon Bell, William D. Strecker
    Computer Structures: What Have We Learned from the PDP-11? [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:138-151 [Conf]
  58. George Z. Chrysos, Joel S. Emer
    Memory Dependence Prediction Using Store Sets. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:142-153 [Conf]
  59. Bernard L. Peuto, Leonard J. Shustek
    An Instruction Timing Model of CPU Performance. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:152-165 [Conf]
  60. Toni Juan, Sanji Sanjeevan, Juan J. Navarro
    Dynamic History-length Fitting: A Third Level of Adaptivity for Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:155-166 [Conf]
  61. David R. Ditzel, David A. Patterson
    Retrospective on High-Level Language Computer Architecture. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:166-173 [Conf]
  62. Karel Driesen, Urs Hölzle
    Accurate Indirect Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:167-178 [Conf]
  63. Kenneth E. Batcher
    Architecture of a Massively Parallel Processor. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:174-179 [Conf]
  64. Shubhendu S. Mukherjee, Mark D. Hill
    Using Prediction to Accelerate Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:179-190 [Conf]
  65. Butler W. Lampson, Kenneth A. Pier
    A Processor for a High-Performance Personal Computer. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:180-194 [Conf]
  66. Mark Oskin, Frederic T. Chong, Timothy Sherwood
    Active Pages: A Computation Model for Intelligent Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:192-203 [Conf]
  67. David Kroft
    Lockup-Free Instruction Fetch/Prefetch Cache Organization. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:195-201 [Conf]
  68. James E. Smith
    A Study of Branch Prediction Strategies. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:202-215 [Conf]
  69. Mark R. Swanson, Leigh Stoller, John B. Carter
    Increasing TLB Reach Using Superpages Backed by Shadow Memory. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:204-213 [Conf]
  70. Xiaogang Qiu, Michel Dubois
    Options for Dynamic Address Translation in COMAs. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:214-225 [Conf]
  71. David A. Patterson, Carlo H. Séquin
    RISC I: A Reduced Instruction Set VLSI Computer. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:216-230 [Conf]
  72. David I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias, Kevin M. Crozier, Ben-Chung Cheng, Patrick R. Eaton, Qudus B. Olaniran, Wen-mei W. Hwu
    Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:227-237 [Conf]
  73. James E. Smith
    Decoupled Access/Execute Computer Architectures. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:231-238 [Conf]
  74. Steven Wallace, Brad Calder, Dean M. Tullsen
    Threaded Multiple Path Execution. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:238-249 [Conf]
  75. Allan Gottlieb, Ralph Grishman, Clyde P. Kruskal, Kevin P. McAuliffe, Larry Rudolph, Marc Snir
    The NYU Ultracomputer - Designing a MIMD, Shared-Memory Parallel Machine. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:239-254 [Conf]
  76. Artur Klauser, Abhijit Paithankar, Dirk Grunwald
    Selective Eager Execution on the PolyPath Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:250-259 [Conf]
  77. James R. Goodman
    Using Cache Memory to Reduce Processor-Memory Traffic. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:255-262 [Conf]
  78. Sanjay J. Patel, Marius Evers, Yale N. Patt
    Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:262-271 [Conf]
  79. Joseph A. Fisher
    Very Long Instruction Word Architectures and the ELI-512. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:263-273 [Conf]
  80. Freddy Gabbay, Avi Mendelson
    The Effect of Instruction Fetch Bandwidth on Value Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:272-281 [Conf]
  81. Joel S. Emer, Douglas W. Clark
    A Characterization of Processor Performance in the VAX-11/780. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:274-283 [Conf]
  82. David H. Albonesi
    Dynamic IPC/Clock Rate Optimization. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:282-292 [Conf]
  83. Mark S. Papamarcos, Janak H. Patel
    A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:284-290 [Conf]
  84. James E. Smith, Andrew R. Pleszkun
    Implementation of Precise Interupts in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:291-299 [Conf]
  85. Yinong Zhang, George B. Adams III
    Performance Modeling and Code Partitioning for the DS Architecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:293-304 [Conf]
  86. Wen-mei W. Hwu, Yale N. Patt
    HPSm, a High Performance Restricted Data Flow Architecture Having Minimal Functionality. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:300-308 [Conf]
  87. Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee
    Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:306-317 [Conf]
  88. Marco Annaratone, Emmanuel A. Arnould, Thomas R. Gross, H. T. Kung, Monica S. Lam, Onat Menzilcioglu, Ken Sarocky, Jon A. Webb
    Warp Architecture and Implementation. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:309-319 [Conf]
  89. Gheith A. Abandah, Edward S. Davidson
    Effects of Architectural and Technological Advances on the HP/Convex Exemplar's Memory and Communication Performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:318-329 [Conf]
  90. Michel Dubois, Christoph Scheurich, Faye A. Briggs
    Memory Access Buffering in Multiprocessors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:320-328 [Conf]
  91. Gurindar S. Sohi, Sriram Vajapeyam
    Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:329-336 [Conf]
  92. Matthias A. Blumrich, Richard Alpert, Yuqun Chen, Douglas W. Clark, Stefanos N. Damianakis, Cezary Dubnicki, Edward W. Felten, Liviu Iftode, Kai Li, Margaret Martonosi, Robert A. Shillner
    Design Choices in the SHRIMP System: An Empirical Study. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:330-341 [Conf]
  93. William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills
    Architecture of a Message-Driven Processor. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:337-344 [Conf]
  94. Vijayaraghavan Soundararajan, Mark Heinrich, Ben Verghese, Kourosh Gharachorloo, Anoop Gupta, John L. Hennessy
    Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:342-355 [Conf]
  95. Jean-Loup Baer, Wen-Hann Wang
    On the Inclusion Properties for Multi-Level Cache Hierarchies. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:345-352 [Conf]
  96. Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz
    An Evaluation of Directory Schemes for Cache Coherence. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:353-362 [Conf]
  97. Sanjeev Kumar, Christopher B. Wilkerson
    Exploiting Spatial Locality in Data Caches Using Spatial Footprints. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:357-368 [Conf]
  98. Sarita V. Adve, Mark D. Hill
    Weak Ordering - A New Definition. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:363-375 [Conf]
  99. William L. Lynch, Gary Lauterbach, Joseph I. Chamdani
    Low Load Latency Through Sum-Addressed Memory (SAM). [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:369-379 [Conf]
  100. Kourosh Gharachorloo, Daniel Lenoski, James Laudon, Phillip B. Gibbons, Anoop Gupta, John L. Hennessy
    Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:376-387 [Conf]
  101. Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, David A. Wood
    Analytic Evaluation of Shared-memory Systems with ILP Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:380-391 [Conf]
  102. Norman P. Jouppi
    Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache Prefetch Buffers. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:388-397 [Conf]
  103. Gregory M. Papadopoulos, David E. Culler
    Monsoon: An Explicit Token-Store Architecture. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:398-407 [Conf]
  104. Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu
    IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:408-417 [Conf]
  105. Daniel Lenoski, James Laudon, Truman Joe, David Nakahira, Luis Stevens, Anoop Gupta, John L. Hennessy
    The DASH Prototype: Implementation and Performance. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:418-429 [Conf]
  106. Thorsten von Eicken, David E. Culler, Seth Copen Goldstein, Klaus E. Schauser
    Active Messages: A Mechanism for Integrated Communication and Computation. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:430-440 [Conf]
  107. Christopher J. Glass, Lionel M. Ni
    The Turn Model for Adaptive Routing. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:441-450 [Conf]
  108. Tse-Yu Yeh, Yale N. Patt
    Alternative Implementations of Two-Level Adaptive Branch Prediction. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:451-461 [Conf]
  109. David J. Kuck, Edward S. Davidson, Duncan H. Lawrie, Ahmed H. Sameh, Chuan-Qi Zhu
    The Cedar System and an Initial Performance Study. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:462-472 [Conf]
  110. Matthias A. Blumrich, Kai Li, Richard Alpert, Cezary Dubnicki, Edward W. Felten, Jonathan Sandberg
    Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:473-484 [Conf]
  111. Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy
    The Stanford FLASH Multiprocessor. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:485-496 [Conf]
  112. Steven K. Reinhardt, James R. Larus, David A. Wood
    Tempest and Typhoon: User-Level Shared Memory. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:497-508 [Conf]
  113. Anant Agarwal, Ricardo Bianchini, David Chaiken, Kirk L. Johnson, David A. Kranz
    The MIT Alewife Machine: Architecture and Performance. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:509-520 [Conf]
  114. Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykumar
    Multiscalar Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:521-532 [Conf]
  115. Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
    Simultaneous Multithreading: Maximizing On-Chip Parallelism. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:533-544 [Conf]
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NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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