Conferences in DBLP
Gordon Bell , William D. Strecker Computer Structures: What Have We Learned from the PDP-11? [Citation Graph (0, 0)][DBLP ] Conf ] Helmut Kerner , Werner Beyerle A PMS Level Language for Performance Evaluation Modelling (V-PMS). [Citation Graph (0, 0)][DBLP ] Conf ] M. Moalla , Gabriele Saucier , Joseph Sifakis , M. Zachariades A Design Tool for the Multilevel Description and Simulation of Systems of Interconnected Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan Allen A Course in Computer Structures. [Citation Graph (0, 0)][DBLP ] Conf ] George E. Rossmann The IEEE Computer Society Task Force on Computer Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence C. Widdoes Jr. The Minerva Multi-Micropocessor. [Citation Graph (0, 0)][DBLP ] Conf ] R. G. Arnold A Hierarchical, Restructurable Multi-Microprocessor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Robert McGill , John Steinhoff A Multimicroprocessor Approach to Numerical Analysis: An Application to Gaming Problems. [Citation Graph (0, 0)][DBLP ] Conf ] John E. Jensen , Jean-Loup Baer A Model of Interference in a Shared Resource Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] C. Leung , David Misunas , A. Neczwid , Jack B. Dennis A Computer Simulation Facility for Packet Communication Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] S. L. Rege Cost, Performance and Size Tradeoffs for Different Levels in a Memory Hierarchy. [Citation Graph (0, 0)][DBLP ] Conf ] Paul E. Dworak , Alice C. Parker An Input Interface for Real-Time Digital Sound Generation System. [Citation Graph (0, 0)][DBLP ] Conf ] Michael C. Mulder , Patrick P. Fasang A Microprocessor Oriented Data Acquisition and Control System for Power System Control. [Citation Graph (0, 0)][DBLP ] Conf ] H. M. Gladney , Gerd Hochweller Multiprogramming for Real-Time Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Theodore H. Kehl Basil Architecture - An HLL Minicomputer. [Citation Graph (0, 0)][DBLP ] Conf ] Harold W. Lawson Jr. Function Distribution in Computer System Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Chris A. Vissers Interface, A Dispersed Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Thomasian , Algirdas Avizienis A Design Study of a Shared Resource Computing System. [Citation Graph (0, 0)][DBLP ] Conf ] Warwick S. Ford , V. Carl Hamacher Hardware Support for Inter-Process Communication and Processor Sharing. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrich Trambacz , Georg Hyla A Taxonomy of Display Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo B. Fernández , Rita C. Summers , Charles D. Coleman Architecture Support for System Protection. [Citation Graph (0, 0)][DBLP ] Conf ] James W. Gault , Alice C. Parker The Design of a User-Programmable Digital Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Werner E. Kluge Traversing Binary Tree Structures with Shift Register Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Serge Fournier , Ming T. Liu System Design of a Grammar-Programmable High-Level Language Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Philip S. Liu , Frederic J. Mowle Selection Schemes for Dynamically Microcoding Fortran Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Ch. Kuznia , R. Kober , H. Kopp SMS 101 - A Structured Multimicroprocessor System with Deadlock-Free Operation Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Samuel H. Fuller , Daniel P. Siewiorek , R. J. Swan The Design of a Multi-Micro-Computer System. [Citation Graph (0, 0)][DBLP ] Conf ] Cecil C. Reames , Ming T. Liu Design and Simulation of the Distributed Loop Computer Network (DLCN). [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Franchi Distribution of Functions and Control in RPCNET. [Citation Graph (0, 0)][DBLP ] Conf ] Larry D. Wittie Efficient Message Routing in Mega-Micro-Computer Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Terry A. Welch An Investigation of Descriptor Oriented Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Edward A. Feustel Tagged Architecture and the Semantics of Programming Languages: Extensible Types. [Citation Graph (0, 0)][DBLP ] Conf ] Alan P. Batson , Robert E. Brundage , John P. Kearns Design Data for Algol-60 Machines. [Citation Graph (0, 0)][DBLP ] Conf ] William D. Strecker Cache Memories for PDP-11 Family Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Janak H. Patel , Edward S. Davidson Improving the Throughput of a Pipeline by Insertion of Delays. [Citation Graph (0, 0)][DBLP ] Conf ] A. M. Abd-Alla , Laird H. Moffett On-Line Architecture Tuning Using Microcapture. [Citation Graph (0, 0)][DBLP ] Conf ] Leonard D. Healy A Character-Oriented Context-Addressed Segment Sequential Storage. [Citation Graph (0, 0)][DBLP ] Conf ] J. A. Bush , G. Jack Lipovski , Stanley Y. W. Su , J. K. Watson , S. J. Ackerman Some Implementations of Segment Sequential Functions. [Citation Graph (1, 0)][DBLP ] Conf ] M. DeMartinis , G. Jack Lipovski , Stanley Y. W. Su , J. K. Watson A Self-Managing Secondary Memory System. [Citation Graph (1, 0)][DBLP ] Conf ] Samuel H. Fuller Price/Performance Comparison of C.mmp and the PDP-10. [Citation Graph (0, 0)][DBLP ] Conf ] 