Conferences in DBLP
Yaohan Chu Architecture of a Hardware Data Interpreter. [Citation Graph (0, 0)][DBLP ] Conf ] Subrata Dasgupta , Simon Fraser The Design of Some Language Constructs for Horizontal Microprogramming. [Citation Graph (0, 0)][DBLP ] Conf ] E. Douglas Jensen , Richard Y. Kain The Honeywell Modular Microprogram Machine: M3. [Citation Graph (0, 0)][DBLP ] Conf ] Richard R. Ramseyer , Andries van Dam A Multi-Microprocessor Implementation of a General Purpose Pipelined CPU. [Citation Graph (0, 0)][DBLP ] Conf ] C. V. Ravi , Torben Moller A Hierarchical Microcomputer System for Hardware and Software Development. [Citation Graph (0, 0)][DBLP ] Conf ] J. Archer Harris , David R. Smith Hierarchical Multiprocessor Organizations. [Citation Graph (0, 0)][DBLP ] Conf ] K. Murakami , S. Nishikawa , M. Soto Poly-Processor System Analysis and Design. [Citation Graph (0, 0)][DBLP ] Conf ] Guy Mazaré A Few Examples of How to Use a Symmetrical Multi-Micro-Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Peter M. Kogge The Microprogramming of Pipelined Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Howard Jay Siegel The Universality of Various Types of SIMD Machine Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] B. Ramakrishna Rau , George E. Rossman The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units. [Citation Graph (0, 0)][DBLP ] Conf ] S. R. Ahuja , J. Robert Jump A Modular Memory Scheme for Array Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Leonard S. Haynes The Architecture of an ALGOL 60 Computer Implemented with Distributed Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Herbert Sullivan , Theodore R. Bashkow A Large Scale, Homogeneous, Fully Distributed Parallel Machine, I. [Citation Graph (1, 0)][DBLP ] Conf ] Herbert Sullivan , Theodore R. Bashkow , David Klappholz A Large Scale, Homogeneous, Fully Distributed Parallel Machine, II. [Citation Graph (0, 0)][DBLP ] Conf ] G. Jack Lipovski On Virtual Memories and Micronetworks. [Citation Graph (0, 0)][DBLP ] Conf ] Jon C. Strauss , Kenneth J. Thurber Considerations for New Tactical Computer Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth J. Thurber , Peter C. Patton , Robert C. Deward , Jon C. Strauss , Thomas W. Petschauer An Advanced Tactical Computer Concept. [Citation Graph (0, 0)][DBLP ] Conf ] Gary J. Nut Microprocessor Implementation of a Parallel Processor. [Citation Graph (1, 0)][DBLP ] Conf ] Paul E. Dworak , Alice C. Parker , Richard Blum The Design and Implementation of a Real-Time Sound Generation System. [Citation Graph (0, 0)][DBLP ] Conf ] Alice C. Parker , Andrew W. Nagle Hardware/Software Tradeoffs in A Variable Word Width, Variable Queue Length Buffer Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard L. Peuto , Leonard J. Shustek An Instruction Timing Model of CPU Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Cornelis H. Hoogendoorn Reduction of Memory Interference in Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dan W. Hammerstrom , Edward S. Davidson Information Content of CPU Memory Referencing Behavior. [Citation Graph (0, 0)][DBLP ] Conf ] Ming T. Liu , Cecil C. Reames Message Communication Protocol and Operation System Design for the Distributed Loop Computer Network (DLCN). [Citation Graph (0, 0)][DBLP ] Conf ] G. H. Poujoulat Architecture of the Corail Building Block System. [Citation Graph (0, 0)][DBLP ] Conf ] H. L. Tredennick , Terry A. Welch High-Speed Buffering for Variable Length Operands. [Citation Graph (0, 0)][DBLP ] Conf ] 